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PDF SSD2825G44 Data sheet ( Hoja de datos )
| Número de pieza | SSD2825G44 | |
| Descripción | MIPI Master Bridge | |
| Fabricantes | SOLOMON | |
| Logotipo |  |
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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD2825G44
Advance Information
MIPI Master Bridge
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD2825G44 Rev 1.5
P 1/161 Dec 2012
Copyright © 2012 Solomon Systech Limited
1 page  
10.4.18 Victual Channel Identifier (VC) ............................................................................................................109
10.4.19 Data Type (DT) .....................................................................................................................................109
10.5 OPERATING MODES ...........................................................................................................................................113
10.5.1 Video Mode ...............................................................................................................................................113
10.5.2 State machine operation............................................................................................................................128
10.5.3 D-PHY operation ......................................................................................................................................128
10.5.4 PLL ...........................................................................................................................................................129
10.5.5 Clock Source Example ..............................................................................................................................130
11 EXTERNAL INTERFACE.................................................................................................. 131
11.1 SPI INTERFACE 8 BIT 4 WIRE.............................................................................................................................132
11.2 SPI INTERFACE 8 BIT 3 WIRE.............................................................................................................................134
11.2.1 3 or 4 wires 8bit SPI read back sequence for 0xFF register which is stored MIPI read back data .........136
11.3 SPI INTERFACE 24 BIT 3 WIRE...........................................................................................................................138
11.3.1 3 wires 24bit SPI read back sequence for 0xFF register which is stored MIPI read back data...............140
12 MAXIMUM RATINGS........................................................................................................ 142
13 RECOMMENDED OPERATING CONDITIONS ........................................................... 143
14 DC CHARACTERISTICS................................................................................................... 144
15 AC CHARACTERISTICS................................................................................................... 146
15.1 8 BIT 4 WIRE SPI INTERFACE TIMING................................................................................................................147
15.2 8 BIT 3 WIRE SPI INTERFACE TIMING................................................................................................................148
15.3 24 BIT 3 WIRE SPI INTERFACE TIMING..............................................................................................................149
15.4 RGB INTERFACE TIMING...................................................................................................................................150
15.5 RESET TIMING .................................................................................................................................................151
15.6 TX_CLK TIMING ..............................................................................................................................................151
16 POWER UP SEQUENCE .................................................................................................... 152
17 POWER OFF SEQUENCE ................................................................................................. 153
18 EXAMPLE FOR SYSTEM SLEEP IN AND OUT ........................................................... 154
18.1 SERIAL LINK DATA ORDER................................................................................................................................155
19 PACKAGE INFORMATION.............................................................................................. 158
19.1 DIMENSION FOR SSD2825G44 ..........................................................................................................................158
SSD2825G44
Rev 1.5 P 5/161 Dec 2012
Solomon Systech
5 Page 
3 ORDERING INFORMATION
Table 3-1: Ordering Information
Ordering Part Number
SSD2825G44
Package Form
64 WFBGA (in Tray form)
4 BLOCK DIAGRAM
Figure 4-1: Block Diagram
Clock and Reset module
Long and Short Data Buffer 0 or 1
PLL
ECC/CRC 0 or 1
Protocol Control
Unit 0 or 1
Packet Processing Unit 0 or 1
D-PHY Controller 0 or 1
Analog Transceiver
SSD2825G44
Rev 1.5 P 11/161 Dec 2012
Solomon Systech
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SSD2825G44.PDF ] | |
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