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Número de pieza PHPT60606NY
Descripción NPN high power bipolar transistor
Fabricantes NXP Semiconductors 
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PHPT60606NY
60 V, 6 A NPN high power bipolar transistor
8 December 2014
Product data sheet
1. General description
NPN high power bipolar transistor in a SOT669 (LFPAK56) Surface-Mounted Device
(SMD) power plastic package.
PNP complement: PHPT60606PY
2. Features and benefits
High thermal power dissipation capability
High temperature applications up to 175 °C
Reduced Printed Circuit Board (PCB) requirements comparing to transistors in DPAK
High energy efficiency due to less heat generation
AEC-Q101 qualified.
3. Applications
Power management
Load switch
Linear mode voltage regulator
Backlighting applications
Relay replacement
Motor drive
4. Quick reference data
Table 1.
Symbol
VCEO
IC
ICM
RCEsat
Quick reference data
Parameter
Conditions
collector-emitter
voltage
open base
collector current
peak collector current single pulse; tp ≤ 1 ms
collector-emitter
saturation resistance
IC = 6 A; IB = 600 mA; pulsed;
tp ≤ 300 µs; δ ≤ 0.02; Tamb = 25 °C
Min Typ Max Unit
- - 60 V
- - 6A
- - 14 A
- 34 45 mΩ
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PHPT60606NY pdf
NXP Semiconductors
PHPT60606NY
60 V, 6 A NPN high power bipolar transistor
103
Zth(j-a)
(K/W)
102
10
duty cycle = 1
0.75
0.33
0.5
0.2
0.1
0.05
0.02
1
0
0.01
aaa-014786
10-1
10-5
10-4
10-3
FR4 PCB, standard footprint
10-2
10-1
1
10 102 103
tp (s)
Fig. 2. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
102 aaa-014787
Zth(j-a)
(K/W)
10
duty cycle = 1
0.75
0.5
0.33
0.2
0.1
0.05
1
0.01
0.02
0
10-1
10-5
10-4
10-3
10-2
FR4 PCB, mounting pad for collector 6 cm2
10-1
1
10 102 103
tp (s)
Fig. 3. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
PHPT60606NY
Product data sheet
All information provided in this document is subject to legal disclaimers.
8 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved
5 / 16

5 Page





PHPT60606NY arduino
NXP Semiconductors
PHPT60606NY
60 V, 6 A NPN high power bipolar transistor
12. Package outline
Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads
SOT669
L1
HD
E A A2 C
b2 c2
mounting
base
D1
L2
12 34
e b wA
1/2 e
X
c
E1
b3
b4
A
A1
C
detail X
(A3)
q
L
yC
Dimensions (mm are the original dimensions)
0
scale
5 mm
θ
8°
0°
Unit(1)
A A1 A2 A3 b b2 b3 b4 c c2 D(1) D1(1) E(1) E1(1) e H L L1
max 1.20 0.15 1.10
0.50 4.41 2.2
mm nom
0.25
min 1.01 0.00 0.95
0.35 3.62 2.0
0.9 0.25 0.30 4.10 4.20
0.7 0.19 0.24 3.80
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
5.0
4.8
3.3 6.2 0.85 1.3
1.27
3.1 5.8 0.40 0.8
Outline
version
References
IEC
JEDEC
JEITA
European
projection
SOT669
MO-235
L2 w y
1.3
0.25 0.1
0.8
sot669_po
Issue date
11-03-25
13-02-27
Fig. 14. Package outline LFPAK56; Power-SO8 (SOT669)
PHPT60606NY
Product data sheet
All information provided in this document is subject to legal disclaimers.
8 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved
11 / 16

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