PDF LTC2246H Data sheet ( Hoja de datos )

Número de pieza	LTC2246H
Descripción	ADC
Fabricantes	Linear Technology
Logotipo
Hay una vista previa y un enlace de descarga de LTC2246H (archivo pdf) en la parte inferior de esta página. Total 18 Páginas
No Preview Available ! FEATURES n Sample Rate: 25Msps n –40°C to 125°C Operation n Single 3V Supply (2.8V to 3.5V) n Low Power: 75mW n 74.5dB SNR n 90dB SFDR n No Missing Codes n Flexible Input: 1VP-P to 2VP-P Range n 575MHz Full Power Bandwidth S/H n Clock Duty Cycle Stabilizer n Shutdown and Nap Modes n Pin Compatible Family LTC2246H (14-Bit), LTC2226H (12-Bit) n 48-Pin (7mm × 7mm) LQFP Package APPLICATIONS n Automotive n Industrial n Wireless and Wired Broadband Communication LTC2246H 14-Bit, 25Msps 125°C ADC In LQFP DESCRIPTION The LTC®2246H is a 14-bit 25Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2246H is perfect for demanding imaging and communications applications with AC performance that includes 74.5dB SNR and 90dB SFDR. DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION REFH REFL ANALOG INPUT FLEXIBLE REFERENCE + INPUT S/H – CLOCK/DUTY CYCLE CONTROL CLK 14-BIT PIPELINED ADC CORE CORRECTION LOGIC OUTPUT DRIVERS OVDD D13 • • • D0 OGND 2246H TA01 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 Typical INL, 2V Range 4096 8192 CODE 12288 16384 2246H TA01b 2246hfb 1 1 page LTC2246H ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 25MHz, input range = 2VP-P with differential drive, unless otherwise noted. Note 5: Integral nonlinearity is deﬁned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code ﬂickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 25MHz, input range = 1VP-P with differential drive. Note 9: Recommended operating conditions. TYPICAL PERFORMANCE CHARACTERISTICS Typical INL, 2V Range, 25Msps 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 CODE 12288 16384 2246H G01 Typical DNL, 2V Range, 25Msps 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 4096 8192 CODE 12288 16384 2246H G02 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 25Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 2 4 6 8 10 12 FREQUENCY (MHz) 2246H G03 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 25Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 2 4 6 8 10 12 FREQUENCY (MHz) 2246H G04 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 25Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 2 4 6 8 10 12 FREQUENCY (MHz) 2246H G05 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 25Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 2 4 6 8 10 12 FREQUENCY (MHz) 2246H G06 2246hfb 5 5 Page LTC2246H APPLICATIONS INFORMATION DAC to produce a residue. The residue is ampliﬁed and output by the residue ampliﬁer. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H ampliﬁer which drives the ﬁrst pipelined ADC stage. The ﬁrst stage acquires the output of the S/H dur- ing this high phase of CLK. When CLK goes back low, the ﬁrst stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and ﬁfth stages, resulting in a ﬁfth stage residue that is sent to the sixth stage ADC for ﬁnal evaluation. Each ADC stage following the ﬁrst has additional range to accommodate ﬂash and ampliﬁer offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2246H CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, LTC2246H VDD 15Ω AIN+ VDD 15Ω AIN– CPARASITIC 1pF CPARASITIC 1pF CSAMPLE 4pF CSAMPLE 4pF CLK Figure 2. Equivalent Input Circuit 2246H F02 the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the har- monic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to VCM or a low noise reference voltage between 1V and 1.5V. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pins (Pins 44, 45) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pins must be bypassed to ground close to the ADC with a 2.2μF or greater capacitor. 2246hfb 11 11 Page

Páginas	Total 18 Páginas
PDF Descargar	[ Datasheet LTC2246H.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
LTC2246	(LTC2246 - LTC2248) 65/40/25Msps Low Power 3V ADCs	Linear Technology
LTC2246H	ADC	Linear Technology

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar