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PDF MC14530B Data sheet ( Hoja de datos )
| Número de pieza | MC14530B | |
| Descripción | DUAL 5-INPUT MAJORITY LOGIC GATE | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 5-Input Majority
Logic Gate
The MC14530B dual five–input majority logic gate is constructed with
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Combinational and sequential logic expressions are
easily implemented with the majority logic gate, often resulting in fewer
components than obtainable with the more basic gates. This device can also
provide numerous logic functions by using the W and some of the logic (A
thru E) inputs as control inputs.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΕ Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD DC Supply Voltage
– 0.5 to + 18.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout Input or Output Voltage (DC or Transient)
Iin, Iout Input or Output Current (DC or Transient),
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎper Pin
– 0.5 to VDD + 0.5
± 10
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
500 mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature (8–Second Soldering)
260 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
LOGIC TABLE
INPUTS A B C D E
WZ
For all combinations of inputs where three or 0 1
more inputs are logical “0”.
10
For all combinations of inputs where three or 0 0
more inputs are logical “1”.
11
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14530B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
W BLOCK DIAGRAM
6
1A
2B
3 C M5
4D
5E
7
Z
* Z = M5
Z = M5
Z = M5
W = (ABC+ABD+ABE+ACD+
W = (ACE+ADE+BCD+BCE+
W = (BDE+CDE) W
9A
10 B
11 C M5
12 D
13 E
15
Z
14
W
* M5 is a logical “1” if any three or more
inputs are logical “1”.
Exclusive NOR Exclusive OR
TRUTH TABLE
M5 W
00
01
10
11
Z
1
0
0
1
VDD = PIN 16
VSS = PIN 8
MC14530B
1
1 page  
BASIC COMBINATIONAL FUNCTIONS
W
1
A
B
C
D
E
W
0
A
ZB
M5
C
D
E
Z
M5
W
1
1
0
A
B
C
W
1
1
1
A
B
C
5–INPUT MAJORITY GATES
W
0
Z
1
0
M3
A
B
C
3–INPUT MAJORITY GATES
W
0
Z
1
1
OR3
A
B
C
Z
M3
Z
NOR3
3–INPUT OR GATE
W
1
0
0
A
B
C
3–INPUT AND GATE
Z
AND3
3–INPUT NOR GATE
W
0
0
0
A
B
C
Z
NAND3
3–INPUT NAND GATE
5–INPUT MAJORITY LOGIC GATE APPLICATIONS
Each package labeled M5 is a single majority logic gate
using five inputs, A thru E, and one output Z.
1. Majority Logic Gate Array
yielding the symmetric function
of 1 thru 7 variables true, out
of 7 input variables (X1... X7)
(e.g., if any two–input variables
are true (logical “1”), Z1 and
Z2 are true (logical “1”)
0A
0
B
C M5
D
E
Z7
0
A
B
C M5
D
E
Z6
0
0
M5
A
B
C M5
D
E
Z5
DOUBLING THE WEIGHT OF INPUT VARIABLE A
BY TYING IT TO ANY TWO INPUTS
WW
A
A
B
Z
(AB + AC + AD + BCD) W
C
D
To W
S0 A
S1 B
S2 C
S3 D
S4 E
W
To
To A
S0 B
S1 C
S2 D
S3 E
CORRELATION OF MULTIPLE SAMPLES
WITH A TEST BIT
Z
CORRELATION OF 60%, 80%, 100%
The gate will have a “1” output if
the test bit To matches or corre-
lates with 3, 4 or 5 of the sample
bits S0–S4.
Z CORRELATION OF 75%, 100%
0
0
0
1
1
1
W
To
To A
To B
S0 C
S1 D
S2 E
Z
CORRELATION OF 100%
X1 X3
X2
M5
M5
M5
0
M5
M5
1
M5
1
1
M5
X4 X5
A
B
C M5
D
E
A
B
C M5
D
E
1A
B
C
D
M5
E
1A
1B
C M5
D
E
X6 X7
Z4
Z3
Z2
Z1
MOTOROLA CMOS LOGIC DATA
MC14530B
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC14530B.PDF ] | |
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