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PDF TSL2583 Data sheet ( Hoja de datos )
| Número de pieza | TSL2583 | |
| Descripción | LIGHT-TO-DIGITAL CONVERTER | |
| Fabricantes | TAOS | |
| Logotipo |  |
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Features
D 30y More Sensitive Than the TSL2560/61
Device
D Approximates Human Eye Response
D Programmable ALS Interrupt Function with
User-Defined Upper and Lower Threshold
Settings
D 16-Bit Digital Output with I2C Fast-Mode at
400 kHz
D Programmable Analog Gain and Integration
Time Supporting 1,000,000-to-1 Dynamic
Range
D Available in Ultra-Small 1.25 mm y 1.75 mm
Chipscale Package and Small 2 mm y 2 mm
Flat No-Lead Package
D Automatically Rejects 50/60-Hz Lighting
Ripple
D Low Quiescent Current 3 mA in Power
Down Mode
D RoHS Compliant
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134A − JULY 2012
PACKAGE CS
6-LEAD CHIPSCALE
(TOP VIEW)
VDD 1
ADDR SEL 2
GND 3
6 SDA
5 INT
4 SCL
PACKAGE FN
DUAL FLAT NO-LEAD
(TOP VIEW)
VDD 1
ADDR SEL 2
GND 3
6 SDA
5 INT
4 SCL
Package Drawings are Not to Scale
Applications
D Ambient Light Sensor (ALS) for Display
Brightness Control
End Products and Market Segments
D HDTVs
D Laptops and Tablets
D Mobile Handsets
D Monitors
Description
The TSL2581 and TSL2583 are very-high sensitivity light-to-digital converters that transform light intensity to
a digital signal output capable of direct I2C interface. Each device combines one broadband photodiode (visible
plus infrared) and one infrared-responding photodiode on a single CMOS integrated circuit capable of providing
a near-photopic response over an effective 16-bit dynamic range (16-bit resolution). Two integrating ADCs
convert the photodiode currents to a digital output that represents the irradiance measured on each channel.
This digital output can be input to a microprocessor where illuminance (ambient light level) in lux is derived using
an empirical formula to approximate the human eye response. The TSL2581 device supports a traditional level
style interrupt that remains asserted until the firmware clears it.
While useful for general purpose light sensing applications, the TSL2581/83 devices are designed particularly
for displays (LCD, OLED, etc.) with the purpose of extending battery life and providing optimum viewing in
diverse lighting conditions. Display panel backlighting, which can account for up to 50 to 60 percent of total
platform power, can be automatically managed. Both devices are also ideal for controlling keyboard illumination
based upon ambient lighting conditions. Illuminance information can further be used to manage exposure
control in digital cameras. The TSL2581/83 devices are ideal in notebook/tablet PCs, LCD monitors, flat-panel
televisions, cell phones, and digital cameras. In addition, other applications include street light control, security
lighting, sunlight harvesting, machine vision, and automotive instrumentation clusters.
The LUMENOLOGY r Company
r
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972r) 673-0759
www.taosinc.com
Copyright E 2012, TAOS Inc.
1
1 page  
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
AC Electrical Characteristics, VDD = 3 V, TA = 255C (unless otherwise noted)
PARAMETER†
TEST CONDITIONS
MIN
t(CONV)
f(SCL)
t(BUF)
t(HDSTA)
Conversion time
Clock frequency
Bus free time between start and stop condition
Hold time after (repeated) start condition. After
this period, the first clock is generated.
2.7
0
1.3
0.6
t(SUSTA)
Repeated start condition setup time
t(SUSTO)
Stop condition setup time
t(HDDAT)
Data hold time
t(SUDAT)
Data setup time
t(LOW)
SCL clock low period
t(HIGH)
SCL clock high period
tF Clock/data fall time
tR Clock/data rise time
Ci Input pin capacitance
† Specified by design and characterization; not production tested.
0.6
0.6
0
100
1.3
0.6
TAOS134A − JULY 2012
TYP MAX UNIT
688 ms
400 kHz
μs
μs
μs
μs
0.9 μs
ns
μs
μs
300 ns
300 ns
10 pF
PARAMETER MEASUREMENT INFORMATION
SCL
t(BUF)
SDA
t(LOW)
t(R)
VIH
VIL
t(HDSTA)
t(HDDAT)
VIH
VIL
t(F)
t(HIGH) t(SUSTA)
t(SUDAT)
P
Stop
Condition
S
Start
Condition
SCL
S
Start
Stop
t(LOWSEXT)
SCLACK
SCLACK
t(LOWMEXT)
t(LOWMEXT)
t(LOWMEXT)
SDA
Figure 1. Timing Diagrams
t(SUSTO)
P
The LUMENOLOGY r Company
r
www.taosinc.com
r
Copyright E 2012, TAOS Inc.
5
5 Page 
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134A − JULY 2012
Control Register (00h)
The CONTROL register primarily used to power the TSL258x device up and down as shown in Table 4.
Table 4. Control Register
Bit : 7 6 5 4 3 2 1 0
Address
00h
Reserved
ADRCe_sINvTR ADC_VALID
Reserved
ADC_EN POWER
Reset
00h
FIELD
Reserved
ADC_INTR
ADC_VALID
Reserved
ADC_EN
POWER
BIT DESCRIPTION
7:6 Reserved. Write as 0.
5 ADC Interrupt. Read only. Indicates that the device is asserting an interrupt.
4 ADC Valid. Read only. Indicates that the ADC channel has completed an integration cycle.
3:2 Reserved. Write as 0.
1
ADC Enable. This field enables the two ADC channels to begin integration. Writing a 1 activates the ADC
channels, and writing a 0 disables the ADCs.
0 Power On. Writing a 1 powers on the device, and writing a 0 turns it off.
NOTE: ADC_EN and POWER must be asserted before the ADC changes will operate correctly. After POWER is asserted, a 2-ms delay is
required before asserting ADC_EN.
NOTE: The TSL258x device registers should be configured before ADC_EN is asserted.
Timing Register (01h)
The TIMING register controls the internal integration time of the ADC channels in 2.7-ms increments. The
TIMING register defaults to 00h at power on.
Table 5. Timing Register
Bit :
Address
01h
7
FIELD
BIT
ATIME
7:0
6 54 321 0
ATIME
Reset
00h
DESCRIPTION
Integration Cycles. Specifies the integration time in 2.7-ms intervals. Time is expressed as a 2’s
complement number. So, to quickly work out the correct value to write: (1) determine the number of
2.7-ms intervals required, and (2) then take the 2’s complement. For example, for a 1 × 2.7-ms interval,
0xFF should be written. For 2 × 2.7-ms intervals, 0xFE should be written. The maximum integration time
is 688.5 ms (00000001b).
Writing a 0x00 to this register is a special case and indicates manual timing mode. See CONTROL and
MANUAL INTEGRATION TIMER Registers for other device options related to manual integration.
INTEG_CYCLES
−
1
2
19
37
74
148
255
TIME
Manual integration
2.7 ms
5.4 ms
51.3 ms
99.9 ms
199.8 ms
399.6 ms
688.5 ms
00000000
11111111
11111110
11101101
11011011
10110110
01101100
00000001
VALUE
NOTE: The Send Byte protocol cannot be used when ATIME is greater than 127 (for example ATIME[7] = 1) since the upper bit is set aside for
write transactions in the COMMAND register.
The LUMENOLOGY r Company
r
Copyright E 2012, TAOS Inc.
www.taosinc.com
r
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TSL2583.PDF ] | |
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