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PDF PL613-05 Data sheet ( Hoja de datos )
| Número de pieza | PL613-05 | |
| Descripción | 3 Output Clock IC | |
| Fabricantes | PhaseLink Corporation | |
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(Preliminary)PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
FEATURES
DESCRIPTION
• Designed for PCB space savings with 3 low-power The PL613-05 is an advanced triple PLL design
Programmable PLLs and 3 distinct clock outputs.
based on PhaseLink’s PicoPLL, world’s smallest
• Low-power consumption (<10µA when PDB is
activated)
programmable clock, technology. This flexible
programmable architecture is ideal for high
• Output frequency:
performance, low-power, low-cost applications. When
o <110MHz @ 1.8V operation
using the power down (PDB) feature the PL613-05
o <166MHz @ 2.5V operation
consumes less than 10 µA of power. Besides its small
o <200MHz @ 3.3V operation
form factor and 3 distinct outputs that can reduce
•
Input frequency:
o Fundamental Crystal: 10MHz to 40MHz
o Reference Input: 10MHz to 200MHz
overall system costs, the PL613-05 offers superior
phase noise, jitter and power consumption
performance.
• Programmable I/O pins can be configured as
Output Enable (OE), Power Down (PDB) inputs, or
Clock output.
• Disabled outputs programmable as HiZ or
Active Low
• Single 1.8V to 3.3V, ±10% power supply
• Operating temperature range from -40°C to 85°C
• Available in GREEN/RoHS compliant SOP-8L package.
PIN CONFIGURATION
XIN, FIN
CLK2, OEM^, PDB^
VDD
CLK0
1
2
3
4
8 XOUT
7 VDD
6 CLK1
5 GND
SOP-8L
^ Denotes internal pull up
BLOCK DIAGRAM
FREF
XIN/FIN
XOUT
Xtal FREF Programmable VCO1
OSC
PLL1
Odd/Even
Divider
(5-bits)
OEM
PDB
Programmable Function
Programmable VCO2
PLL2
FREF
Programmable VCO3
PLL3
Odd/Even
Divider
(5-bits)
Odd/Even
Divider
(5-bits)
%1, %2,
%4, %8
%1, %2,
%4, %8
CLK1
CLK0
CLK2, OEM, PDB
2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 1
1 page  
(Preliminary)PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD -0.5 4.6
V
Input Voltage Range
VI
-0.5 VDD+0.5
V
Output Voltage Range
VO
-0.5 VDD+0.5
V
Soldering Temperature (Green package)
260 °C
Data Retention @ 85°C
10 Year
Storage Temperature
TS -65 150 °C
Ambient Operating Temperature*
-40 85 °C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN. TYP. MAX. UNITS
Crystal Input Frequency (XIN) Fundamental Crystal
10 40 MHz
@ VDD =3.3V
200
Input (FIN) Frequency
@ VDD =2.5V
10 166 MHz
@ VDD =1.8V
110
Input (FIN) Signal Amplitude Internally AC coupled (High Frequency)
0.9
VDD Vpp
Input (FIN) Signal Amplitude
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
0.1
VDD Vpp
@ VDD =3.3V
200
Output Frequency
@ VDD =2.5V
166 MHz
@ VDD =1.8V
110
Settling Time
At power-up (after VDD increases over 1.62V)
2 ms
Output Enable Time
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
10 ns
2 ms
VDD Sensitivity
Frequency vs. VDD +/-10%
-2 2 ppm
Output Rise Time
15pF Load, 10/90% VDD, High Drive, 3.3V
1.2 1.7 ns
Output Fall Time
15pF Load, 90/10% VDD, High Drive, 3.3V
1.2 1.7 ns
Duty Cycle
PLL Enabled, @ VDD /2, High Drive
45 50 55 %
Period Jitter, Pk-to-Pk*
Configuration Dependant, with capacitive
(10,000 samples)
decoupling between VDD and GND.
* Note: Jitter performance depends on the programming parameters.
300 ps
2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PL613-05.PDF ] | |
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