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PDF CY27H010 Data sheet ( Hoja de datos )
| Número de pieza | CY27H010 | |
| Descripción | 128K x 8 High-Speed CMOS EPROM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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fax id: 30231CY27H010
CY27H010
128K x 8 High-Speed CMOS EPROM
Features
• CMOS for optimum speed/power
• High speed
— tAA = 25 ns max. (commercial)
— tAA = 35 ns max. (military)
• Low power
— 275 mW max.
— Less than 85 mW when deselected
• Byte-wide memory organization
• 100% reprogrammable in thewindowed package
• EPROM technology
• Capable of withstanding >2001V static discharge
• Available in
— 32-pin PLCC
— 32-pin TSOP-I
— 32-pin, 600-mil plastic or hermetic DIP
— 32-pin hermetic LCC
Functional Description
The CY27H010 is a high-performance, 1-megabit CMOS
EPROM organized in 128 Kbytes. It is available in indus-
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
ADDRESS
DECODER
PROGRAMMABLE
ARRAY
MULTIPLEXER
POWER DOWN
CE
OUTPUT ENABLE
OE DECODER
try-standard 32-pin, 600-mil DIP, LCC, PLCC, and TSOP-I
packages. These devices offer high-density storage com-
bined with 40-MHz performance. The CY27H010 is available
in windowed and opaque packages. Windowed packages al-
low the device to be erased with UV light for 100% re-
programmability.
The CY27H010 is equipped with a power-down chip enable
(CE) input and output enable (OE). When CE is deasserted,
the device powers down to a low-power stand-by mode. The
OE pin three-states the outputs without putting the device into
stand-by mode. While CE offers lower power, OE provides a
more rapid transition to and from three-stated outputs.
The memory cells utilize proven EPROM floating-gate technol-
ogy and byte-wide intelligent programming algorithms. The
EPROM cell requires only 12.75 V for the supervoltage and
low programming current allows for gang programming. The
device allows for each memory location to be tested 100%,
because each location is written to, erased, and repeatedly
exercised prior to encapsulation. Each device is also tested
for AC performance to guarantee that the product will meet DC
and AC specification limits after customer programming.
The CY27H010 is read by asserting both the CE and the OE
inputs. The contents of the memory location selected by the
address on inputs A16–A0 will appear at the outputs O7–O0.
Pin Configurations
DIP
Top View
O0
VPP 1
32 VCC
A16 2
31 PGM
O1
A15 3
30 NC
A12 4
29 A14
O2
A7 5
A6 6
28 A13
27 A8
O3
A5 7
A4 8
26 A9
25 A11
A3 9
24 OE
A2 10
23 A10
O4
A1 11
22 CE
A0 12
21 O7
O0 13
20 O6
O5
O1 14
19 O5
O2 15
18 O4
O6
GND 16
17 O3
LCC/PLCC
H010–2
O7 Top View
H010–1
4 3 2 1 32 31 30
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
O0 13
21 O7
14151617 181920
H010–3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 1994 – Revised March 1997
1 page  
CY27H010
Table 1. Programming Electrical Characteristics
Parameter
Description
VPP
IPP
VIHP
VILP
VCCP
Programming Power Supply
Programming Supply Current
Programming Input Voltage HIGH
Programming Input Voltage LOW
Programming VCC
Min.
12.5
3.0
–0.5
6.0
Max.
13
50
VCC
0.4
6.5
Unit
V
mA
V
V
V
Table 2. Mode Selection
Mode
Read
Output Disable
Stand-by
Program
Program Verify
Program Inhibit
Signature Read (MFG)[9]
Signature Read (DEV)[9]
Notes:
7.
8.
XVHcVa=n1b2eV±V0IL.5Vor VIH.
9. A1 − A8 and A10 − A16 = VIL
CE
VIL
X
VIH
VILP
VILP
VIHP
VIL
VIL
OE
VIL
VIH
X
VIHP
VILP
X
VIL
VIL
PGM
X
X
X
VILP
VIHP
X
X
X
Pin Function[7]
VPP
A0
X A0
XX
XX
VPP
VPP
VPP
VIH
VIH
A0
A0
X
VIL
VIH
A9
A9
X
X
A9
A9
X
VHV[8]
VHV[8]
Data
Dout
High Z
High Z
Din
Dout
High Z
34H
1DH
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY27H010.PDF ] | |
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