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| Número de pieza | MTA9ASF51272PZ | |
| Descripción | DDR4 SDRAM RDIMM | |
| Fabricantes | Micron | |
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4GB (x72, ECC, SR) 288-Pin DDR4 RDIMM
Features
DDR4 SDRAM RDIMM
MTA9ASF51272PZ – 4GB
Features
• DDR4 functionality and operations supported as
defined in the component data sheet
• 288-pin, registered dual in-line memory module
(RDIMM)
• Fast data transfer rates: PC4-2400, PC4-2133, or
PC4-1866
• 4GB (512 Meg x 72)
• VDD = 1.20V (typical)
• VPP = 2.5V (typical)
• VDDSPD = 2.2–3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Low-power auto self refresh (LPASR)
• Data bus inversion (DBI) for data bus
• On-die VREFDQ generation and calibration
• Single-rank
• On-board I2C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Figure 1: 288-Pin RDIMM (MO-309, R/C-D)
Module height: 31.25mm (1.23in)
Options
• Operating temperature
– Commercial (0°C ≤ TOPER ≤ +95°C)
• Package
– 288-pin DIMM (halogen-free)
• Frequency/CAS latency
– 0.83ns @ CL = 16 (DDR4-2400)
– 0.93ns @ CL = 15 (DDR4-2133)
– 1.07ns @ CL = 13 (DDR4-1866)
Marking
None
Z
-2G4
-2G1
-1G9
Table 1: Key Timing Parameters
Speed
Grade
-2G4
-2G1
-1G9
Industry
Data Rate (MT/s)
Nomenclature CL = 18 CL = 16 CL = 15 CL = 14 CL = 13 CL = 12 CL = 11 CL = 9
PC4-2400
2400 2400 2133 1866 1866 1600 1600 1333
PC4-2133
– 2133 2133 1866 1866 1600 1600 1333
PC4-1866
– – – 1866 1866 1600 1600 1333
tRCD
(ns)
13.32
13.5
13.5
tRP
(ns)
13.32
13.5
13.5
tRC
(ns)
45.32
46.5
47.5
PDF: 09005aef85197107
asf9c512x72pz.pdf - Rev. C 10/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
4GB (x72, ECC, SR) 288-Pin DDR4 RDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4
modules. All pins listed may not be supported on this module. See Functional Block Di-
agram for pins specific to this module.
Table 5: Pin Descriptions
Symbol
Ax
Type
Input
A10/AP
Input
A12/BC_n
ACT_n
BAx
BGx
Input
Input
Input
Input
C0, C1, C2
(RDIMM/LRDIMM on-
ly)
Input
CKx_t
CKx_c
CKEx
Input
Input
CSx_n
Input
Description
Address inputs: Provide the row address for ACTIVATE commands and the column address for
READ/WRITE commands in order to select one location out of the memory array in the respec-
tive bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;
see individual entries in this table.) The address inputs also provide the op-code during the
MODE REGISTER SET command. A17 is only defined for x4 SDRAM.
Auto precharge: A10 is sampled during READ and WRITE commands to determine whether an
auto precharge should be performed on the accessed bank after a READ or WRITE operation.
(HIGH = auto precharge; LOW = no auto precharge.) A10 is sampled during a PRECHARGE com-
mand to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank
addresses.
Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst
chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst- chopped.) See Com-
mand Truth Table in the DDR4 component data sheet.
Command input: ACT_n defines the ACTIVATE command being entered along with CS_n. The
input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and
A14. See Command Truth Table.
Bank address inputs: Define the bank (with a bank group) to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command.
Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configura-
tions. x16-based SDRAM only has BG0.
Chip ID: These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for
x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16
configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,
CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,
are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used
as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of
the command code.
Clock: Differential clock inputs. All address, command, and control input signals are sampled
on the crossing of the positive edge of CK_t and the negative edge of CK_c.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device
input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is
asynchronous for self refresh exit. After VREFCA has become stable during the power-on and ini-
tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE
must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,
CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE
and RESET#) are disabled during self refresh.
Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external
rank selection on systems with multiple ranks. CS_n is considered part of the command code
(CS2_n and CS3_n are not used on UDIMMs).
PDF: 09005aef85197107
asf9c512x72pz.pdf - Rev. C 10/14 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
5 Page 
4GB (x72, ECC, SR) 288-Pin DDR4 RDIMM
General Description
General Description
High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal
memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM
devices have four internal bank groups consisting of four memory banks each, provid-
ing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank
groups consisting of four memory banks each, providing a total of eight banks. DDR4
SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with
an interface designed to transfer two data words per clock cycle at the I/O pins. A single
READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-
wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-
wide, one-half-clock-cycle data transfers at the I/O pins.
DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data
and CK_t and CK_c to capture commands, addresses, and control signals. Differential
clocks and data strobes ensure exceptional noise immunity for these signals and pro-
vide precise crossing points to capture input signals.
Fly-By Topology
DDR4 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock, con-
trol, command, and address pin on each DRAM is connected to a single trace and ter-
minated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-
nals can be easily accounted for by using the write-leveling feature of DDR4.
Registering Clock Driver Operation
Registered DDR4 SDRAM modules use a registering clock driver device consisting of a
register and a phase-lock loop (PLL). The device complies with the JEDEC DDR4 RCD01
Specification.
To reduce the electrical load on the host memory controller's command, address, and
control bus, Micron's RDIMMs utilize a DDR4 registering clock driver (RCD). The RCD
presents a single load to the controller while redriving signals to the DDR4 SDRAM de-
vices, which helps enable higher densities and increase signal integrity. The RCD also
provides a low-jitter, low-skew PLL that redistributes a differential clock pair to multiple
differential pairs of clock outputs.
Control Words
The RCD device(s) used on DDR4 RDIMMs and LRDIMMs contain configuration regis-
ters known as control words, which the host uses to configure the RCD based on criteria
determined by the module design. Control words can be set by the host controller
through either the DRAM address and control bus or the I2C bus interface. The RCD I2C
bus interface resides on the same I2C bus interface as the module temperature sensor
and EEPROM.
Parity Operations
The RCD includes a parity-checking function that can be enabled or disabled in control
word RC0E. The RCD receives a parity bit at the DPAR input from the memory control-
PDF: 09005aef85197107
asf9c512x72pz.pdf - Rev. C 10/14 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
11 Page | ||
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