PDF IS25WQ080 Data sheet ( Hoja de datos )

Número de pieza	IS25WQ080
Descripción	8 Mbit bit Single Operating Voltage Serial Flash Memory
Fabricantes	ISSI
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No Preview Available ! 8 Mbit bit Single Operating Voltage Serial Flash Memory With 104 MHz Dual- or Quad-Output SPI Bus Interface IS25WQ080 FEATURES • Single Power Supply Operation - Low voltage range: 1.65 V – 2 V • Memory Organization - IS25WQ080: 1024K x 8 (8 Mbit) • Cost Effective Sector/Block Architecture - 8Mb : Uniform 4KByte sectors / Sixteen uniform 64KByte blocks • Serial Peripheral Interface (SPI) Compatible - Supports single-, dual- or quad-output - Supports SPI Modes 0 and 3 - Maximum 33 MHz clock rate for normal read - Maximum 104 MHz clock rate for fast read - Maximum 208MHz clock rate equivalent Dual SPI - Maximum 416MHz clock rate equivalent Quad SPI • Byte Program Operation - Typical 8 us/Byte • Page Program (up to 256 Bytes) Operation - Maximum 0.7 ms per page program • Sector, Block or Chip Erase Operation - Sector Erase (4KB)150 ms (Max) - Block Erase (32K/64KB)0.5S (Max) - Chip Erase 6s (8Mb) (Max) •Deep power-down mode 1uA (Typ) PRELIMINARY DATASHEET • Low Power Consumption - Max 15 mA active read current - Max 20 mA program/erase current - Max 50uA standby current • Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin • Software Write Protection - The Block Protect (BP3, BP2, BP1, BP0) bits allow partial or entire memory to be configured as read-only • High Product Endurance - Guaranteed 100,000 program/erase cycles per single sector - Minimum 20 years data retention • Industrial Standard Pin-out and Package - 8-pin PDIP - 8-pin 208mil SOIC - 8-pin 150mil SOIC - 8-pin 150mil VVSOP - 8-contact WSON - 16-pin 300mil SOP - Lead-free (Pb-free) package Additional 256-byte Security information one-time programmable (OTP) area GENERAL DESCRIPTION The IS25WQ080 are 8Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quad- output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, ranging from 1.65 Volt to 2.0 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers. The IS25WQ080 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks. The IS25WQ080 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are offered in 8-pin SOIC 150mil/208mil, 8-contact WSON, 8-pin PDIP and 8-pin VVSOP 150mil, . Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/18/2012 1 1 page IS25WQ080 SPI MODES DESCRIPTION Multiple IS25WQ080 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 1. The devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) The difference between these two modes is the clock polarity when the SPI master is in Stand-by mode: the serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure 2. For both modes, the input data is latched on the rising edge of Serial Clock (SCK), and the output data is available from the falling edge of SCK. Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices) SPI Interface with (0,0) or (1,1) SDI SDI SCK SPI Master (i.e. Microcontroller) CS3 CS2 CS1 SCK SO SI SCK SO SI SCK SO SI SPI Memory Device CE# WP# HOLD# SPI Memory Device CE# WP# HOLD# SPI Memory Device CE# WP# HOLD# Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as Figure 2. SPI Modes Supported SCK Mode 0 (0,0) SCK Mode 3 (1,1) SI Input mode SO MSb Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/18/2012 MSb 5 5 Page IS25WQ080 Table 9. Instruction Set Instruction Name RDID JEDEC ID READ RDMDID WREN WRDI RDSR WRSR READ FAST_READ FRDO FRDIO FRQO FRQIO MR PAGE_ PROG Hex Code Abh 9Fh 90h 06h 04h 05h 01h 03h 0Bh 3Bh BBh 6Bh Ebh FFh 02h Operation Read Manufacturer and Product ID/ release deep power down mode Read Manufacturer and Product ID by JEDEC ID Command Read Manufacturer and Device ID Write Enable Write Disable Read Status Register Write Status Register Read Data Bytes from Memory at Normal Read Mode Read Data Bytes from Memory at Fast Read Mode Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Mode Reset Page Program Data Bytes Into Memory SECTOR_ER BLOCK_ER (32KB) BLOCK_ER (64KB) CHIP_ER Dual page program Quad page program D7h/ 20h 52h D8h C7h/ 60h A2h 32h Sector Erase Block Erase Block Erase Chip Erase Page Program Data Bytes Into Memory with Dual interface Page Program Data Bytes Into Memory with Quad interface Power down Program information Raw Read information Raw Program/Erase Suspend Program/Erase Resume RDFR B9h B1h 4Bh 75h/ B0h 7Ah/ 30h 07h Program 256 bytes of Security area Read 256 bytes of Security area Suspend during the program/erase Resume program/erase Read function register Comman Maximum d Cycle Frequency 4 Bytes 104 MHz 1 Byte 4 Bytes 1 Byte 1 Byte 1 Byte 2 Bytes 4 Bytes 5 Bytes 5 Bytes 3 Bytes 5 Bytes 2 Bytes 2 Byte 4 Bytes + 256B 4 Bytes 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 33 MHz 104 MHz 104 MHz 104MHz 104 MHz 104MHz 104MHz 104 MHz 104 MHz 4 Bytes 4 Bytes 1 Byte 104 MHz 104 MHz 104 MHz 4 Bytes + 256B 4 Bytes 104MHz 104MHz 104MHz 104 MHz 4 Bytes 33 MHz 1 byte 104MHz 1 byte 104MHz 1 byte 104MHz HOLD OPERATION HOLD# is used in conjunction with CE# to select the IS25WQ080. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to Sl will be ignored while SO is in the high impedance state. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/18/2012 11 11 Page

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