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PDF CXD3422GA Data sheet ( Hoja de datos )

Número de pieza CXD3422GA
Descripción Timing Generator and Signal Processor
Fabricantes Sony 
Logotipo Sony Logotipo



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CXD3422GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description
The CXD3422GA is a timing generator and CCD
signal processor IC for the ICX284, ICX432/434
CCD image sensor.
96 pin LFLGA (Plastic)
Features
Timing generator functions
Horizontal drive frequency 18 to 24.3MHz
(Base oscillation frequency 36 to 48.6MHz)
Supports frame readout/draft (sextuple speed)/
AF (Auto focus drive) (ICX432 mode)
Supports frame readout/draft (quadruple speed)/
AF (Auto focus drive) (ICX434 mode)
High-speed/low-speed shutter function
Horizontal and vertical drivers for CCD image
sensor
CCD signal processor functions
Correlated double sampling
Programmable gain amplifier (PGA) allows gain
adjustment over a wide range (–6 to +42dB)
10-bit A/D converter
Chip Scale Package (CSP):
CSP allows vast reduction in the CCD camera
block footprint
Applications
Digital still cameras
Applicable CCD Image Sensors
ICX284 (Type 1/2.7, 2020K pixels)
ICX432 (Type 1/2.7, 3240K pixels)
ICX434 (Type 1/3.2, 2020K pixels)
Absolute Maximum Ratings
Supply voltage
VDDa, VDDb, VDDc, VDDd VSS – 0.3 to +7.0 V
VDDe, VDDf, VDDg
VSS – 0.3 to +4.0 V
VL
–10.0 to VSS
V
VH VL – 0.3 to +26.0 V
Input voltage (analog)
VIN VSS – 0.3 to VDD + 0.3 V
Input voltage (digital)
VI VSS – 0.3 to VDD + 0.3 V
Output voltage
VO1 VSS – 0.3 to VDD + 0.3 V
VO2 VL – 0.3 to VSS + 0.3 V
VO3 VL – 0.3 to VH + 0.3 V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Recommended Operating Conditions
Supply voltage
VDDa, VDDb, VDDc, VDDd,
VDDe, VDDf, VDDg
3.0 to 3.6
VM 0.0
VH 14.5 to 15.5
VL –7.0 to –8.0
Operating temperature
Topr –20 to +75
V
V
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02125-PS

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CXD3422GA pdf
CXD3422GA
Pin
No.
Symbol
E8 AVDD2
E9 AVDD1
F1 DVSS2
F2 DVSS3
F3 DVDD2
F7 PBLKI
F8 XSHDI
F9 XSHPI
G1 ADCLKI
G2 CLPOBI
G3 CLPDMI
G7 PBLK
G8 XSHD
G9 XSHP
H1 ADCLK
H2 CLPOB
H3 CLPDM
H7 TEST1
H8 VDD4
H9 VDD3
J1 CKI
J2 CKO
J3 VSS4
J7 VSS3
J8 H1
J9 H2
K1 OSCO
K2 MCKO
K3 VDD5
K7 VDD2
K8 RG
K9 VSS2
L1 OSCI
L2 SSI1
I/O Description
CCD signal processor block analog power supply.
CCD signal processor block analog power supply.
CCD signal processor block digital GND.
CCD signal processor block digital GND.
CCD signal processor block digital power supply.
I
Pulse input for horizontal and vertical blanking period pulse cleaning.
(Schmitt trigger)
I CCD data level sample-and-hold pulse input. (Schmitt trigger)
I CCD precharge level sample-and-hold pulse input. (Schmitt trigger)
I Clock input for analog/digital conversion. (Schmitt trigger)
I CCD optical black signal clamp pulse input. (Schmitt trigger)
I CCD dummy signal clamp pulse input. (Schmitt trigger)
O Pulse output for horizontal and vertical blanking period pulse cleaning.
O CCD data level sample-and-hold pulse output.
O CCD precharge level sample-and-hold pulse output.
O
Clock output for analog/digital conversion.
Logical phase adjustment possible using the serial interface data.
O
CCD optical black signal clamp pulse output.
Horizontal and vertical OB pattern charge possible using the serial interface data.
O CCD dummy signal clamp pulse output.
I
Timing generator block test input 1.
Normally fix to GND. (With pull-down resistor)
Timing generator block digital power supply. (Power supply for CDS block)
Timing generator block digital power supply. (Power supply for H1/H2)
I Inverter input.
O Inverter output.
Timing generator block digital GND.
Timing generator block digital GND.
O CCD horizontal register clock output.
O CCD horizontal register clock output.
O Inverter output for oscillation. When not used, leave open or connect a capacitor.
O System clock output for signal processor IC.
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block digital power supply. (Power supply for RG)
O CCD reset gate pulse output.
Timing generator block digital GND.
I Inverter input for oscillation. When not used, fix to low.
I Timing generator block serial interface data input. Schmitt trigger input.
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CXD3422GA arduino
CXD3422GA
AC Characteristics
AC characteristics between the serial interface clocks
SSI1
SCK1
SEN1
SEN1
0.2VDDd
0.8VDDd
0.8VDDd
0.2VDDd
ts3
ts1
th1
0.8VDDd
ts2
Symbol
ts1
th1
ts2
ts3
(Within the recommended operating conditions)
Definition
SSI1 setup time, activated by the rising edge of SCK1
SSI1 hold time, activated by the rising edge of SCK1
SCK1 setup time, activated by the rising edge of SEN1
SEN1 setup time, activated by the rising edge of SCK1
Min. Typ. Max. Unit
20 ns
20 ns
20 ns
20 ns
Serial interface clock internal loading characteristics (1)
VD
HD
Example: During frame mode
V1A
HD
V1A
SEN1
0.2VDDd
0.8VDDd
ts1
Enlarged view
th1
0.2VDDd
Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal
period during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
Symbol
ts1
th1
(Within the recommended operating conditions)
Definition
SEN1 setup time, activated by the falling edge of HD
SEN1 hold time, activated by the falling edge of HD
Min. Typ. Max. Unit
0 ns
123 µs
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