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PDF RPLIS-2048-EX Data sheet ( Hoja de datos )
| Número de pieza | RPLIS-2048-EX | |
| Descripción | 2048 x 1 Linear Image Sensor | |
| Fabricantes | Panavision Imaging | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RPLIS-2048-EX (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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RPLIS-2048-EX
ONE TE C H N O L O G Y PLACE – HOMER, NEW YORK 13077
TEL: +1 607 749 2000 FAX: +1 607 749 3295 www.PanavisionImaging.com / [email protected]
RPLIS-2048-EX 2048 x 1 Linear Image Sensor Datasheet
Key Features
• High resolution
o Linear sensor with 2048 pixels, including 12
optical black pixels
o 4 µm X 32 µm pixels on a 4 µm pixel pitch
o 32 µm X 8192 µm imaging area
o Fill factor >99%
• Special Features
o On-chip Auto Dynamic ThresholdTM * (ADT)
with digital output – eliminates external ADC
o Full frame electronic shutter
o On-chip correlated double sampling
o Black pixel clamping removes global pixel
offsets
o Dynamic Power ControlTM ** minimizes power
consumption for each operating mode
• High sensitivity and dynamic range
o 12/24 µV/electron programmable conversion
gain
o 1.7V full scale range
o 65 dB dynamic range
• Ease of application
o Single 3.0 V supply voltage
o Only a clock and a start pulse needed for
operation
o Programmable setup register for device mode
selection
• Multiple operating modes
o Analog video output
o Digital comparator output
o ADTTM digital output and analog output
o Ultra low-power standby mode
o Short and Normal exposure modes
P/N RPLIS-2048-EX B-LG
Packaged Imager Photo
Actual Size
2060
8192 um
14 4 um
13
12
O ptic al
B lac k
1
PDS0012_1.vsd
32 um
Figure 1: Pixel Structure Drawing
* Auto Dynamic ThresholdingTM (ADT) is a trademark of Panavision Imaging, LLC
** Dynamic Power ControlTM is a trademark of Panavision Imaging, LLC
ACS® is a registered trademark of Panavision Imaging, LLC
PDS0039 Rev F
© Panavision Imaging 2008 All rights reserved.
Subject to change without notice.
Page 1 of 17
1 page  
RPLIS-2048-EX
TOP VIEW
TM 1
16 CLK
LPM 2
15 STRT
/Dout 3
14 DVAL
AVDD 4
13 DVDD
AGND 5
12 DGND
Vout 6
11 SEN
THR 7
10 SDIN
ATI 8
9 SCLK
Figure 2: Pin-out diagram, top view
Absolute Maximum and Environmental Specifications
Table 4. Absolute Maximum Specifications
Supply voltage range, VDD[1] …….……………………………...……………………… 0 V to 6.0 V
Digital input current range, IIN….…………………………………………..………….. –4 mA to 4 mA
Digital output current range, IOUT…………………………….………………………... –4 mA to 4 mA
† Exceeding the ranges specified under “absolute maximum ratings” can damage the device. The values given are for stress ratings only.
Operation of the device at conditions other than those indicated above, is not implied. Exposing the device to absolute maximum rated conditions
for extended periods may affect device reliability and performance.
Notes:
1. Voltage values are with respect to the device GND terminal.
Table 5. Environment Specifications
Operating case temperature range, TCASE [1]…………….…………………………...
Operating free-air temperature range, TA …………….………………………….…..
Storage temperature range…………………………………………………………….
Humidity range, RH………………………………………….…………………………..
Lead temperature 1.5 mm (0.06 inch) from case for 45 seconds..………….……..
–10°C to 70°C
–10°C to 50°C
–20°C to 85°C
0-100%, non-condensing
240°C
PDS0039 Rev F
© Panavision Imaging 2008 All rights reserved.
Subject to change without notice.
Page 5 of 17
5 Page 
RPLIS-2048-EX
ADT Readout Timing
The readout timing in ADT mode (Mode 3) is
similar to comparator mode except that there is a
delay in the digital output with respect to DVAL
(Fig. 7). The first digital bit is valid 3, 6 or 9 clock
CLK
STRT
cycles after DVAL goes high. The number of delayed
clock cycles is programmable and is set through the
programmable setup register. The default is 3 clock
cycles. The delay at the start of the line is also translated
to the end so that the last digital bit is valid 3, 6, or 9
clock cycles after DVAL goes low.
VOUT
DVAL
Line Init.
Black Pixels
Pixel readout
/DOUT
Digital Comparator Output
Figure 6: Comparator Readout Timing.
CLK
STRT
VOUT
DVAL
/Dout
Line Init.
Black Pixels
Pixel readout
3, 6, or 9 clock delay per setting of ADT Pixel Delay
DigDiitgaitlaCl oCmompapraartaotroOr uOtpuutptut
3, 6, or 9
Figure 7: ADT Readout Timing.
Note that /Dout is delayed from Vout and Dval by the ADT pixel delay setting. Also note that the first few pixel data
output on /Dout may not be valid due to the ADT delay.
Line Initialization Detail
Line initialization is 16 clock cycles after STRT has
been sampled as a rising edge. It is used for frame
storage transfers to ACS bus transfer and pixel to frame
storage and other internal operations.
Actual exposure time stops at the first clock cycle
after STRT has been sampled as a rising edge and
the next exposure begins on the next falling edge of
DVAL.
CLK
STRT
Exposure Time
DVAL
Line Initialization, 16 Clock Cycles
Figure 8: Line Initialization Timing
PDS0039 Rev F
© Panavision Imaging 2008 All rights reserved.
Subject to change without notice.
Page 11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet RPLIS-2048-EX.PDF ] | |
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