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PDF SPEAr600 Data sheet ( Hoja de datos )
| Número de pieza | SPEAr600 | |
| Descripción | Embedded MPU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SPEAr600 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SPEAr600
Embedded MPU with dual ARM926 core, flexible memory support,
powerful connectivity features and programmable LCD interface
Datasheet − production data
Features
■ Dual ARM926EJ-S core up to 333 MHz:
– Each with 16 Kbytes instruction cache + 16
Kbytes data cache
■ High performance 8-channel DMA
■ Dynamic power saving features
■ Up to 733 DMIPS
■ Memory:
– External DRAM interface: 8/16-bit DDR1-
333 / DDR2 - 666
– 32 Kbytes BootROM / 8 Kbytes internal
SRAM
– Flexible static memory controller (FSMC)
supporting parallel NAND Flash memory
interface, ONFI 1.0 support, internal 1-bit
ECC or external 4-bit ECC
– Serial NOR Flash Memory interface
■ Connectivity:
– 2 x USB 2.0 Host
– USB 2.0 Device
– Giga Ethernet (GMII port)
– I2C and fast IrDA interfaces
– 3 x SSP Synchronous serial peripheral
(SPI, Microwire or TI protocol) ports
– 2 x UART interfaces
■ Peripherals supported:
– TFT/STN LCD controller (resolution up to
1024 x 768 and colors up to 24 bpp)
– Touchscreen support
■ Miscellaneous functions
– Integrated real-time clock, watchdog, and
system controller
– 8-channel 10-bit ADC, 1 Msps
– JPEG codec accelerator
– 10 GPIO bidirectional signals with interrupt
capability
– 10 independent 16-bit timers with
programmable prescaler
■ 32-bit width External local bus (EXPI interface).
PBGA420 (23 x 23 x 2.06 mm)
■ 3 x I2S interfaces for audio features:
– One stereo input and two stereo outputs
(audio 3.1 configuration capable)
■ Customizable logic with 600 Kgate standard
cell array
■ Software:
– System compliant with all operating
systems (including Linux)
Applications
■ The SPEAr® embedded MPU family targets
networked devices used for communication,
display and control. This includes diverse
consumer, business, industrial and life science
applications such as:
– IP phones, thin client computers, printers,
programmable logic controllers, PC
docking stations,
– Medical lab/diagnostics equipment,
wireless access devices, home appliances,
residential control and security systems,
digital picture frames, and bar-code
scanners/readers.
Table 1. Device summary
Order code
Temp.
range
Package
SPEAR600-2 -40 to 85 °C
PBGA420
(23 x 23 x
2.06 mm)
Packing
Tray
May 2012
This is information on a product in full production.
Doc ID 16259 Rev 3
1/97
www.st.com
1
1 page  
SPEAr600
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System reset, master clock, RTC and configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SMI, SSP, UART, FIRDA and I2C pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
USB pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ethernet pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
NAND Flash I/F pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DDR I/F pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LCD I/F pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LVDS I/F pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
EXPI/I2S pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
EXPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table shading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Maximum current and power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Overshoot and undershoot specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Low voltage TTL DC input specification (3 V< VDD <3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . 57
Low voltage TTL DC output specification (3 V< VDD <3.6 V) . . . . . . . . . . . . . . . . . . . . . . . 57
Pull-up and pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
On die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DDR2 read cycle path timings without pad delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DDR2 read cycle timings without pad delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DDR2 write cycle path timings without pad delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DDR2 write cycle timings without pad delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DDR2 command timings without pad delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
EXPI - pad signal assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
EXPI clock and reset parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SOC-master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SOC-slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SOC-master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SOC-slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
CLCD timings with CLCP direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CLCD timings with CLCP divided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Timing characteristics for I2C in high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Timing characteristics for I2C in fast-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Timing characteristics for I2C in standard-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Timing characteristics for 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . 77
Doc ID 16259 Rev 3
5/97
5 Page 
SPEAr600
2 Architecture overview
Architecture overview
Figure 2. shows an example of a typical SPEAr600 based system.
Figure 2. Typical system architecture using SPEAr600
TouchScreen
Internet
Access
Phy
NAND Flash
FLASH
EEPROM
DDR2
DDR1
Debug, Trace
FSMC
SMI
DDR
memory
controller
JTAG
ETM9
SPEAr600
ADC
LCD
controller
ARM 926EJ
up to 333 MHz
ARM 926EJ
up to 333 MHz
MMU
Interrupt/
Syst controller
MMU
Interrupt/
Syst controller
8-Channel DMA 8 KB Embed. SRAM
10 Timers / WD 32 KB Embed. ROM
USB2.0 PHY
device
USB2.0 PHY
Host
USB2.0 PHY
Host
FIdDA
RTC
Clock, Reset
RAS EXPI I/f
I2C
3xI2S Uart1 Uart2 3xSSP
30 MHz 32 kHz
The core of the SPEAr600 is the dual ARM926EJ-S reduced instruction set computer
(RISC) processor.
It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off
between high performance and high code density and includes features for efficient
execution of Java byte codes.
Each ARM CPU:
● Is clocked at a frequency up to 333 MHz
● Embeds 16 Kbytes instruction cache + 16 Kbytes data cache
● Features a memory management unit (MMU) which makes it fully compliant with Linux
and VxWorks operating systems.
The SoC includes three major subsystems logic domains which control the following
function blocks:
Configurable Cell Array Subsystem
This block contains the Reconfigurable Array Subsystem logic (RAS) made by an array of
600Kgate equivalent standard cells freely customizable by means of a few metal and via
mask layer changes during the customization process. The programmable logic allows
reducing the SoC NRE cost, the development cycle time improving the devices time to
Doc ID 16259 Rev 3
11/97
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SPEAr600.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SPEAr600 | Embedded MPU | STMicroelectronics |
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