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PDF N133BGE-P42 Data sheet ( Hoja de datos )
| Número de pieza | N133BGE-P42 | |
| Descripción | TFT LCD Module | |
| Fabricantes | CHIMEI Innolux | |
| Logotipo |  |
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PRODUCT SPECIFICATION
Doc. Number:
ϭʳ Tentative Specification
ϭʳ Preliminary Specification
Ϯʳ Approval Specification
MODEL NO.: N133BGE
SUFFIX: P42
Customer:
APPROVED BY
Name / Title
Note
SIGNATURE
Please return 1 copy for your confirmation with your
signature and comments.
Approved By
ֱᗩ
2012-02-16
15:43:35 CST
Checked By
ඦ֮
2012-02-10
14:46:10 CST
Prepared By
ᑛၺݳ٤
2012-02-10
11:09:37 CST
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PRODUCT SPECIFICATION
3. ABSOLUTE MAXIMUM RATINGS
3.1 ABSOLUTE RATINGS OF ENVIRONMENT (Based on CMI Module)
Item
Symbol
Value
Min. Max.
Unit
Storage Temperature
TST
Operating Ambient Temperature
TOP
Note (1) (a) 90 %RH Max. (Ta <= 40 ºC).
-20
0
+60 ºC
+50 ºC
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The temperature of panel surface should be 0 ºC min. and 60 ºC max.
Relative Humidity (%RH)
100
90
80
Note
(1)
(1), (2)
60
Operating
40
20
10 Storage Range
-40 -20
0 20 40 60 80
Temperature (ºC)
3.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)
High temperature or humidity may reduce the performance of panel. Please store LCD panel within the
specified storage conditions.
Storage Condition: With packing.
Storage temperature range: 25±5 ºC.
Storage humidity range: 50±10%RH.
Shelf life: 30days
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PRODUCT SPECIFICATION
4.4 LVDS INPUT SIGNAL TIMING SPECIFICATIONS
4.4.1 LVDS DC SPECIFICATIONS
Parameter
Symbol
LVDS Differential Input High Threshold VTH(LVDS)
Min.
-
Value
Typ.
-
Max.
+100
LVDS Differential Input Low Threshold VTL(LVDS) -100
-
-
LVDS Common Mode Voltage
VCM 1.125 - 1.375
LVDS Differential Input Voltage
|VID|
100
-
600
LVDS Terminating Resistor
RT - 100 -
Note (1) The parameters of LVDS signals are defined as the following figures.
Unit Note
mV
(1),
VCM=1.2V
mV
(1)
VCM=1.2V
V (1)
mV (1)
Ohm
-
Single Ended
VCM
0V
|VID|
Differential
VTH(LVDS)
0V
VTL(LVDS)
|VID|
4.4.2 LVDS DATA FORMAT
CLK+
Rxin2
Rxin1
Rxin0
T/7
IN20
DE
IN13
B1
IN6
G0
IN19
Vsync
IN12
B0
IN5
R5
IN18
IN17
IN16
Hsync
B5
B4
IN11
IN10
IN9
G5 G4 G3
IN4 IN3
IN2
R4 R3 R2
Signal for 1 DCLK Cycle (T)
IN15
B3
IN8
G2
IN1
R1
IN14
B2
IN7
G1
IN0
R0
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet N133BGE-P42.PDF ] | |
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