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PDF CS35L32 Data sheet ( Hoja de datos )
| Número de pieza | CS35L32 | |
| Descripción | Boosted Class D Amplifier | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS35L32
Boosted Class D Amplifier with Speaker-Protection Monitoring
and Flash LED Drivers
Mono Class D Speaker Amplifier
• Two-level Class G operation:
• Boosted: 5 V nominal
• Bypassed: battery voltage is supplied directly
• 2.5-mA quiescent current, monitors powered down
• 1.7 W into 8 (@ 10% THD+N)
• 102-dB signal-to-noise ratio (SNR, A-weighted)
• Idle channel noise 25 Vrms (A-weighted)
• 90% efficiency
Audio Input and Gain
• One differential analog input
• Speaker gain:
• 9, 12, 15, and 18 dB and mute
• Pop suppression, zero-crossing detect transitions
Flash LED Drivers
• Integrated dual LED drivers using the following:
• Boost supply output voltage
• Dual matched current regulators, 750 mA max each
• Programmable setting for Flash Mode current:
50–750 mA, in 50-mA steps
• Programmable setting for Flash-Inhibit Mode current:
50–350 mA, in 50-mA steps
• Programmable setting for Movie Mode current:
150, 120, 100, 80, 60, 40, 20 mA
• Programmable flash timer setting:
50–500 ms, in 25-ms steps
• Dedicated pin for flash trigger (FLEN)
• Dedicated pin for flash inhibit (FLINH)
• Thermally managed through boost-voltage regulation
(Features continue on page 2)
SPKR
VA
VP VBST SW
IREF+ SUPPLY
FILT+
IN+
IN–
ADC
Current
Sense
Bandgap
Voltage
Generation
VCOM
Current Mode Synchronous
Boost Controller Soft Ramp
Low Battery Management
VREF
Generation
VREF
+
–
9,12,15, or
18 dB + Mute
Class G
I2C Class G Override
Class D Front End
∆Σ Class D Modulator
Short Circuit Protection
Class D Power Stage
SPKR SUPPLY
MCLK
GNDA
Error
Watchdog
Serial Port
Clock Generation
Range
Scaling
LRCK SerSiaClLAK udio/Data Port
ADC
ADC
Level Shifters
FLEN FLINH FLOUT1 FLOUT2/AD0
Control,
Sensing,
and Fault
Protection
Flash LED Current Driver
GNDPLED
Temperature Overtemp
Sensor
Protection
Power
Budgeting
SPKOUT+
SPKOUT–/
VSENSE–
GNDP
VMON ADC VSENSE+
Front End
LP VSENSE–
IMON ADC
Front End
LP
ISENSE+
ISENSE–
I²C Control Port
ISENSE+
ISENSE–/
VSENSE+
SCLK
LRCK
SDOUT
SCL
SDA
RESET
INT
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012–2015
(All Rights Reserved)
DS963F5
AUG ‘15
1 page  
1 Pin Descriptions
CS35L32
1 Pin Descriptions
Ball Name
SDA
SCL
MCLK
SCLK
LRCK
SDOUT
INT
‘‘‘‘‘
A1 A2 A3 A4 A5 A6
SDA
B1
SCL
‘
B2
SDOUT
‘
B3
SCLK
‘
B4
MCLK
‘
B5
FLOUT2/
AD0
‘
B6
VP
INT
RESET
LRCK
GNDPLED
FLOUT1
‘‘‘‘‘
C1 C2 C3 C4 C5 C6
SW
GNDP
GNDP
FLINH
GNDA
VA
‘‘‘‘‘
D1 D2 D3 D4 D5 D6
SW
SPKOUT+ SPKOUT–/
FLEN
IREF+
FILT+
VSENSE–
‘‘‘‘‘
E1 E2 E3 E4 E5 E6
VBST
SPKRSUPPLY
IN–
IN+
ISENSE–/
ISENSE+
VSENSE+
LED
Digital I/O
Audio
Power Supply
General Ground
Boost Converter
Figure 1-1. Top-Down (Through-Package) View—30-Ball WLCSP Package
Ball
Number
Power
Supply
I/O
Table 1-1. Pin Descriptions
Ball Description
Internal
Connection
Driver
Receiver
State at
Reset
Digital I/O
A1 VA I/O I2C Serial Data Input. Serial data for the I2C
serial port
— CMOS Hysteresis Hi-Z
open-drain on CMOS
output
input
A2
VA I I2C Clock Input. Serial clock for the I2C serial
—
port
— Hysteresis Hi-Z
on CMOS
input
A5 VA I Master Clock Source. Clock source for A/D Weak pull-
converters and audio/data serial port (ADSP). down
MCLKINT, derived from MCLK, is used for other (~1 M
blocks (see Section 4.13 and Section 7.7).
— Hysteresis Pulled
on CMOS down
input
A4
VA I/O Serial Clock. Serial shift clock for the serial Weak pull- CMOS
Hysteresis Pulled
audio interface
down
output
on CMOS down
(~1 M
input
B4
VA I/O Left Right Clock. Determines which channel, Weak pull- CMOS
Hysteresis Pulled
left or right, is currently active on the serial down
output
on CMOS down
audio/data lines
(~1 M
input
A3 VA O Serial Audio/Data Output. I²S serial data Weak
CMOS
output used to monitor voltage and current of pull-down output
SPKOUT signal and VP levels
(~1 M
— Pulled
down
B2 VA O Interrupt. Programmable, open-drain, active- — CMOS
— Hi-Z
low programmable interrupt output
open-drain
output
DS963F5
5
5 Page 
CS35L32
3 Characteristics and Specifications
Table 3-7. Signal Monitoring Characteristics
Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, amp gain = 12 dB, 0.1- sense resistor, GNDA = GNDP = 0 V,
TA = +25°C. Measurement bandwidth is 20 Hz to 20 kHz, Fs = 48 kHz, Input Signal = 1 kHz, MCLKINT = 6 MHz, MCLKINT is explained in Section 4.13.1
and Section 7.7.
Parameters
Min Typical Max Units
General ADC characteristics
VSENSE± monitoring
characteristics (VMON)
Power-up time: tPUP(ADC) — 8.5 [1] ms
Data width — 16 — Bits
Dynamic range (unweighted), VSENSE± = ±5.0 V (10 VPP) — 60 — dB 2
Total harmonic distortion + noise, –3.8 dBFS 3 — –60 — dB 2
Full-scale signal input voltage 6.59•VA 6.94•VA 7.29•VA VPP
Common-mode rejection ratio (217 Hz @ 500 mVPP) 4 — 60 — dB 2
Group delay 5 — 7.6/Fs —
s
ISENSE± monitoring
characteristics (IMON)
Data width — 16 — Bits
Dynamic range (unweighted), ISENSE± = ±0.625 A (1.25 APP) — 56 — dB 2
Total harmonic distortion, –29.5 dBFS 6 — –45 — dB 2
Full-scale signal input voltage 1.56•VA 1.64•VA 1.72•VA VPP
VMON-to-IMON isolation 7 — 56 — dB 2
Group delay 8 — 7.6/Fs —
s
VP monitoring characteristics
Data width — 8 — Bits
Voltage resolution (See the equation in Section 4.8.4.) —
35.3
— mV
(FF code) signal input voltage (VP) 2.89•VA 3.05•VA 3.20•VA V
VPMON = 1011 0011
VPMON = 1011 0100
…
VPMON = 1111 1111
VPMON = 0000 0000
—
—
…
—
—
2.8
2.835
…
5.482
5.518
—
—
…
—
—
V
V
…
V
V
1.Typical value is specified with PDN_AMP and PDN_xMON bits initially set. Maximum power-up time is affected by the actual MCLKINT frequency.
2.Parameters given in dB are referred to the applicable typical full-scale voltages. Applies to all THD+N and resolution values in the table
3.VSENSE± THD is measured with the Class D amplifier as the audio source connected to an 8- + 33H speaker load, supplied by a 6.3-VPP, 1-kHz
sine wave, operating under the typical performance test conditions to produce a large, unclipped audio signal. This setup produces a –3.8-dBFS
VMON output. Larger Class D amplifier amplitudes begin to exhibit clipping behavior, increasing distortion of the signal supplied to VSENSE±
4.CMRR test setup for VSENSE±:
VSENSE+
VSENSE–
217 Hz
500 mVPP
DC Offset = 0
5.VMON group delay is measured from the time a signal is presented on the VSENSE± and pins until the MSB of the digitized signal exits the serial
port. Fs is the LRCK rate.
6.For reference, injecting a 125-mVpp fully differential sine wave into the ISENSE± pins (equivalent to a ±0.625 A current with a 0.1- ISENSE resistor)
produces an IMON output of –29.5 dBFS (since typical full-scale is 1.64*VA, in VPP). ISENSE± monitoring THD is measured using the Class D
amplifier as the audio source, which is connected to an 8- + 33-H speaker load, supplied by a 7.0-VPP, 1-kHz sine wave, operating under the
typical performance test conditions to produce a large, unclipped audio signal. This setup produces a –29.5-dBFS amplitude IMON output. Larger
Class D amplifier amplitudes begin to exhibit clipping behavior, increasing the distortion of the signal supplied to ISENSE±.
7.VMON-to-IMON isolation is the error in the current sense due to VMON, expressed relative to full-scale sense current in decibels.
8.IMON group delay is measured from when a signal is presented on the ISENSE± pins until the MSB of the digitized signal exits the serial port. Fs is
the LRCK rate.
Table 3-8. Digital Interface Specifications and Characteristics
Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, GNDA = GNDP = 0 V, TA = +25°C.
Parameters
Symbol
Test Conditions
Min
Max
Input leakage current (per pin) 1,2
FLOUT2/AD0 IIN
FLEN, FLINH, LRCK
——
——
±7.5
±4.5
MCLK, SCLK, SDOUT
SCL, SDA, INT, RESET
——
——
±4.5
±0.1
Input capacitance
VA logic I/Os
IIN
High-level output voltage VOH
——
IOH = –67/–100 A 3 VA–0.2
10
—
Low-level output voltage VOL
High-level input voltage VIH
Low-level input voltage VIL
All outputs, IOL = 67/100 A 3
INT, SDA, IOL = 3 mA
—
—
— 0.70•VA
0.20
0.4
—
— — 0.30•VA
Units
A
A
A
A
pF
V
V
V
V
V
1.Specification includes current through internal pull up/down resistors, where applicable (as defined in Section 1).
2.Leakage current is measured with VA = 1.80 V, VP = 3.60 V, VBST = 3.60 V, and RESET asserted. Each pin is tested while driven high and low.
3.For the ADSP output SDOUT and potential outputs SCLK and LRCK (if M/S = 1), if ADSP_DRIVE = 0 see Section 7.13, IOH and IOL are –100 and
+100 A. If ADSP_DRIVE = 1, IOH and IOL are –67 and +67 A. For other, non-ADSP_DRIVE-affected outputs, IOH and IOLare –100 and +100 A.
DS963F5
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS35L32.PDF ] | |
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