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PDF MAX9280 Data sheet ( Hoja de datos )

Número de pieza MAX9280
Descripción 3.12Gbps GMSL Deserializers
Fabricantes Maxim Integrated Products　
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
General Description
The MAX9276/MAX9280 gigabit multimedia serial link
(GMSL) deserializers receive data from a GMSL serializer
over 50Ω coax or 100Ω shielded twisted pair (STP) cable
and output deserialized data on the LVCMOS outputs.
The MAX9280 has HDCP content protection but other-
wise is the same as the MAX9276. The deserializers pair
with any GMSL serializer capable of coax output including
the MAX9293 HDMI/MHL serializer. When programmed
for STP input they are backward compatible with any
GMSL serializer.
The audio channel supports L-PCM I2S stereo and up to
eight channels of L-PCM in TDM mode. Sample rates of
32kHz to 192kHz are supported with sample depth up to
32 bits.
The embedded control channel operates at 9.6kbps to
1Mbps in UART-UART and UART-I2C modes, and up to
1Mbps in I2C-I2C mode. Using the control channel, a µC
can program serializer, deserializer, and peripheral device
registers at any time, independent of video timing, and
manage HDCP operation (MAX9280). Two GPIO ports
are included, allowing display power-up and switching of
the backlight among other uses. A continuously-sampled
GPI input supports touch-screen controller interrupt
requests in display applications.
For use with longer cables, the deserializers have a pro-
grammable cable equalizer. Programmable spread spec-
trum is available on the parallel output. The serial input
meets ISO 10605 and IEC 61000-4-2 ESD standards.
The core supply is 3.0V to 3.6V and the I/O supply is
1.7V to 3.6V.
The devices are in lead-free, 56-lead, 8mm x 8mm TQFN
and QFND packages with exposed pad and 0.5mm lead
pitch.
Applications
● High-Resolution Automotive Navigation
● Rear-Seat Infotainment
● Megapixel Camera Systems
VIDEO/AUDIO
GMSL
µC SERIALIZER
I2C
VIDEO/AUDIO
MAX9276
MAX9280
720p
DISPLAY
I2C
Benefits and Features
● Ideal for High-Definition Video Applications
• Works with Low-Cost 50Ω Coax Cable and FAKRA
Connectors or 100Ω STP
• 104MHz High-Bandwidth Mode Supports
1920x720p/60Hz Display With 24-Bit Color
• Equalization Allows 15m Cable at Full Speed
• Up to 192kHz Sample Rate And 32-Bit Sample
Depth For 7.1 Channel HD Audio
• Audio Clock from Audio Source or Audio Sink
• Color Lookup-Table for Gamma Correction
• CNTL[3:0] Control Outputs
● Multiple Data Rates for System Flexibility
• Up to 3.12Gbps Serial-Bit Rate
• 6.25MHz to 104MHz Pixel Clock
• 9.6kbps to 1Mbps Control Channel in UART, Mixed
UART/I2C, or I2C Mode with Clock Stretch
Capability
● Reduces EMI and Shielding Requirements
• Programmable Spread Spectrum Reduces EMI
• Tracks Spread Spectrum on Input
• High-Immunity Mode for Maximum Control-
Channel Noise Rejection
● Peripheral Features for System Power-Up and
Verification
• Built-In PRBS Tester for BER Testing of the Serial
Link
• Programmable Choice of 8 Default Device
Addresses
• Two Dedicated GPIO Ports
• Dedicated “Up/Down” GPI for Touch-Screen
Interrupt and Other Uses
• Remote/Local Wake-Up from Sleep Mode
● Meets Rigorous Automotive and Industrial
Requirements
• -40°C to +105°C Operating Temperature
• ±8kV Contact and ±15kV Air ISO 10605 and
IEC 61000-4-2 ESD Protection
Ordering Information appears at end of data sheet.
19-6623; Rev 1; 11/15

1 page




MAX9280 pdf
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
LIST OF FIGURES
Figure 1. Reverse Control Channel Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2a. Test Circuit for Single-Ended Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2. Test Circuit for Differential Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. Worst-Case Pattern Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. Parallel Clock Output Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. Output Rise-and-Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. Deserializer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Output I2S Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. 24-Bit Mode Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. 32-Bit Mode Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. High-Bandwidth Mode Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Audio Channel Input Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. 8-Channel TDM (24-Bit Samples, Padded With Zeros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. 6-Channel TDM (24-Bit Samples, No Padding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Stereo I2S (24-Bit Samples, Padded With Zeros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. Stereo I2S (16-Bit Samples, No Padding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 20. Audio Channel Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22. GMSL UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23. Sync Byte (0x79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 24. ACK Byte (0xC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 25. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . 34
Figure 26. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1) . . . . . . . . 35
Figure 27. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 28. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 29. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 30. Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 31. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 32. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 33. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 34. 2:1 Coax Splitter Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 35. Coax Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 36. LUT Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 37. State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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5 Page





MAX9280 arduino
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
AC Electrical Characteristics
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C.) (Note 10)
PARAMETER
SYMBOL
PARALLEL CLOCK OUTPUT (PCLKOUT)
Clock Frequency
fPCLKOUT
Clock Duty Cycle
Clock Jitter
I2C/UART PORT TIMING
I2C/UART Bit Rate
Output Rise Time
Output Fall Time
I2C TIMING (Figure 4)
DC
tJ
tR
tF
SCL Clock Frequency
fSCL
START Condition Hold Time
tHD:STA
Low Period of SCL Clock
tLOW
High Period of SCL Clock
Repeated START Condition
Setup Time
tHIGH
tSU:STA
CONDITIONS
BWS = low, DRS = ‘1’
BWS = low, DRS = ‘0’
BWS = mid, DRS = ‘1’
BWS = mid, DRS = ‘0’
BWS = high, DRS = ‘1’
BWS = high, DRS = ‘0’
tHIGH/tT or tLOW/tT (Note 6)
Period jitter, peak-to-peak, spread off,
3.12Gbps, PRBS pattern, UI = 1/fPCLKOUT
(Note 6)
30% to 70%, CL = 10pF to 100pF, 1kΩ
pullup to VIOVDD
70% to 30%, CL = 10pF to 100pF, 1kΩ
pullup to VIOVDD
Low fSCL range:
(I2CMSTBT = 010, I2CSLVSH = 10)
Mid fSCL range:
(I2CMSTBT 101, I2CSLVSH = 01)
High fSCL range:
(I2CMSTBT = 111, I2CSLVSH = 00)
fSCL range
Low
Mid
High
Low
Mid
fSCL range
High
VIOVDD = 1.7V to
< 3V (Note 11)
VIOVDD = 3.0V to
3.6V
fSCL range
fSCL range
Low
Mid
High
Low
Mid
High
MIN
8.33
16.66
18.33
36.66
6.25
12.5
40
9.6
20
20
9.6
> 100
> 400
4.0
0.6
0.26
4.7
1.3
0.6
0.5
4.0
0.6
0.26
4.7
0.6
0.26
TYP
50
0.05
MAX UNITS
16.66
104
36.66
104
12.5
78
60
MHz
%
UI
1000
150
kbps
ns
150 ns
100
400
1000
kHz
µs
µs
µs
µs
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