PDF CYRS1544AV18 Data sheet ( Hoja de datos )

Número de pieza	CYRS1544AV18
Descripción	72-Mbit QDR II+ SRAM Two-Word Burst Architecture
Fabricantes	Cypress Semiconductor
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CYRS1542AV18 CYRS1544AV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology Radiation Performance Radiation Data ■ Total Dose =300 Krad ■ Soft error rate (both Heavy Ion and proton) Heavy ions  1 × 10-10 upsets/bit-day with single error correction - double error detection error detection and correction (SEC-DED EDAC) ■ Neutrons = 2.0 × 1014 N/cm2 ■ Dose rate = 2.0 × 109 rad(Si)/sec ■ Dose rate survivability (rad(Si)/sec) = 1.5 × 10^11 rad(Si)/sec ■ Latch up immunity = 120 MeV.cm2/mg (125 °C) Prototyping Options ■ Non qualified CYPT1542AV18 and CTPY1544AV18 devices with same functional and timing characteristics in a 165-ball Ceramic Column Grid Array (CCGA) package Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250-MHz clock for high bandwidth ■ 2-word burst on all accesses ■ Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz) ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ QDR® II operates with 2.0 cycle read latency when delay lock loop (DLL) is enabled ■ Available in × 18 and × 36 configurations ■ Full data coherency, providing most current data ■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD ■ Available in 165-ball CCGA (21 × 25 × 2.83 mm) ■ HSTL inputs and variable drive HSTL output buffers ■ JTAG 1149.1 compatible test access port ■ DLL for accurate data placement Configurations CYRS1542AV18 – 4 M × 18 CYRS1544AV18 – 2 M × 36 Functional Description The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques. The QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words (CYRS1542AV18), or 36-bit words (CYRS1544AV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Description Maximum operating frequency Maximum operating current (concurrent R/W) 250 MHz Unit 250 MHz × 18 1650 mA × 36 1650 Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-60006 Rev. I • San Jose, CA 95134-1709 • 408-943-2600 Revised January 4, 2013 1 page CYRS1542AV18 CYRS1544AV18 Pin Configuration Pin configurations for CYRS1542AV18 and CYRS1544AV18.[1] Figure 1. 165-ball CCGA pinout CYRS1542AV18 (4 M × 18) 12345678 A CQ NC/144M A WPS BWS1 K NC/288M RPS B NC Q9 D9 A NC K BWS0 A C NC NC D10 VSS A A A VSS D NC D11 Q10 VSS VSS VSS VSS VSS E NC NC Q11 VDDQ VSS VSS VSS VDDQ F NC Q12 D12 VDDQ VDD VSS VDD VDDQ G NC D13 Q13 VDDQ VDD VSS VDD VDDQ H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ J NC NC D14 VDDQ VDD VSS VDD VDDQ K NC NC Q14 VDDQ VDD VSS VDD VDDQ L NC Q15 D15 VDDQ VSS VSS VSS VDDQ M NC NC D16 VSS VSS VSS VSS VSS N NC D17 Q16 VSS A A A VSS P NC NC Q17 A A QVLD A A R TDO TCK A A A NC A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI CYRS1544AV18 (2 M × 36) 1234567 A CQ NC/288M A WPS BWS2 K BWS1 B Q27 Q18 D18 A BWS3 K BWS0 C D27 Q28 D19 VSS A A A D D28 D20 Q19 VSS VSS VSS VSS E Q29 D29 Q20 VDDQ VSS VSS VSS F Q30 Q21 D21 VDDQ VDD VSS VDD G D30 D22 Q22 VDDQ VDD VSS VDD H DOFF VREF VDDQ VDDQ VDD VSS VDD J D31 Q31 D23 VDDQ VDD VSS VDD K Q32 D32 Q23 VDDQ VDD VSS VDD L Q33 Q24 D24 VDDQ VSS VSS VSS M D33 Q34 D25 VSS VSS VSS VSS N D34 D26 Q25 VSS A A A P Q35 D35 Q26 A A QVLD A R TDO TCK A A A NC A Note 1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 NC/144M Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Document Number: 001-60006 Rev. I Page 5 of 33 5 Page CYRS1542AV18 CYRS1544AV18 Truth Table CYRS1542AV18 and CYRS1544AV18 [2, 3, 4, 5, 6, 7] Operation Write cycle: Load address on the rising edge of K; input write data on K and K rising edges. Read cycle:(2.0 cycle Latency) Load address on the rising edge of K; wait two cycles; read data on K and K rising edges. NOP: No operation Standby: Clock stopped K RPS WPS DQ L–H X L D(A) at K(t) DQ D(A + 1) at K(t) L–H L X Q(A) at K(t + 2) Q(A + 1) at K(t + 2) L–H H Stopped X H D=X Q = High Z X Previous state D=X Q = High Z Previous state Write Cycle Descriptions CYRS1542AV18 [2, 8] BWS0 L L L L H H H BWS1 L L H H L L H KK Comments L–H – During the data portion of a write sequence Both bytes (D[17:0]) are written into the device. – L–H During the data portion of a write sequence: Both bytes (D[17:0]) are written into the device. L–H – During the data portion of a write sequence Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – L–H During the data portion of a write sequence Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L–H – During the data portion of a write sequence Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – L–H During the data portion of a write sequence Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. L–H – No data is written into the devices during this portion of a write operation. H H – L–H No data is written into the devices during this portion of a write operation. Notes 2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device powers up deselected with the outputs in a tristate condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges. 7. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2 and BWS2 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-60006 Rev. *I Page 11 of 33 11 Page

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