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PDF ALM-2412 Data sheet ( Hoja de datos )
| Número de pieza | ALM-2412 | |
| Descripción | GPS LNA-Filter Front-End Module | |
| Fabricantes | AVAGO | |
| Logotipo |  |
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ALM-2412
GPS LNA-Filter Front-End Module
Data Sheet
Description
Avago Technologies’ ALM-2412 is an LNA module, with
integrated filter, designed for GPS band applications at
1.575GHz. The LNA uses Avago Technologies’ proprietary
GaAs Enhancement-mode pHEMT process to achieve high
gain with very low noise figure and high linearity. Noise
figure distribution is very tightly controlled. A CMOS-com-
patible shutdown pin is included either for turning the
LNA on/off, or for current adjustment. The integrated filter
utilizes an Avago Technologies’ leading-edge FBAR filter
for exceptional rejection at Cell/PCS-Band frequencies.
The ALM-2412 is useable down to 1V operation. It achieves
low noise figure, high gain and linearity even at 1V, making
it suitable for use in critical low-power GPS applications or
during low-battery situations.
Component Image
Surface Mount 3.3x2.1x1.1 mm3 12-lead MCOB
RF_IN 1
Gnd 2
SD 3
2412
XXXXX
9 Gnd
8 FILTER-OUT
7 Gnd
TOP VIEW
Gnd 9
FILTER-OUT 8
Gnd 7
1 RF_IN
2 Gnd
3 SD
BOTTOM VIEW
Note:
Package marking provides orientation and identification
“2412”
= Product Code
First “X”
= Year of manufacture
Second “X”
= Work week of manufacture
Third “X”
= Datecode
Fourth & Fifth “X” = Lot Number
Features
Very Low Noise Figure : 0.85 dB typical
High Gain : 13.5 dB typical
High IIP3 and IP1dB
Exceptional Cell/PCS-Band rejection
Advanced GaAs E-pHEMT Technology
Low external component count
Wide Supply Voltage : 1V to 3.6V
Shutdown current : < 0.1uA
CMOS compatible shutdown pin (SD) current @ 2.8V :
0.1mA
Adjustable current via single external resistor/voltage
Meets MSL3, Lead-Free and Halogen-Free
ESD-protected RF input: 3kV HBM
Small package dimension: 3.3(L)x2.1(W)x1.1(H) mm3
Specifications (Typical performance at 25°C)
At 1.575GHz, Vdd = 2.85V, Idd = 9.0mA
Gain = 13.5 dB
NF = 0.85 dB
IIP3 = +6.1 dBm, IP1dB = +2.2 dBm
S11 = -8.4 dB, S22 =-9.0 dB
Cell-Band Rejection: 53dBc
PCS-Band Rejection: 65dBc
At 1.575GHz, 1.0V supply
S21 = 7.2dB
NF = 1.63dB
Idd = 1.5mA
Application
GPS Band LNA
Attention: Observe precautions for
handling electrostatic sensitive devices.
For RF_IN (Pin 1): ESD Human Body Model = 3 kV
All other pins: ESD Machine Model = 40 V
ESD Human Body Model = 300 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
1 page  
1,4
3 Vdd
R1
C1
L1
Z1
50-Ohms TL
L3
1
C2
L2
12
Input
match
Filter
C9
8
50-Ohms TL
2,4,5,6,7,9,10,11
2 SD
3
R2
C3
Module outline
Figure 2. Demoboard and application schematic diagram
Notes:
The demoboard of Figure 6 is Rogers® RO4350 with typical Dk = 3.48 (@10GHz).
L3 and the module’s internal input pre-match form the input matching network. The module has built-in DC-blocking capacitors at the input and
output.
This circuit demonstrates that very low noise figure is obtainable with standard 0402 chip inductors instead of high-Q wirewound inductors.
C2 and L2 form a matching network at the output of the LNA stage, which can be tuned to optimize gain and return loss. For example, higher gain
can be obtained by increasing the value of C2 but at the expense of stability. Changing the value of L2 can improve the PCS rejection, but impacts
output return loss.
L1 is a choke which isolates the demoboard from external disturbances during measurement. It is not needed in actual application. Likewise, C1
and C3 mitigate the effect of external noise pickup on the Vdd and SD lines respectively. These components are not required in actual operation.
R1 is a stability-enhancing resistor.
C9 is a DC-blocking capacitor. It is also not required in actual operation.
Bias control is achieved by either varying the SD voltage with/ without R2, or fixing the SD voltage to Vdd and adjusting R2 for the desired current.
Typical value for R2 is 10k Ohms for 9mA total current at Vdd = 2.85V and Vsd = +2.60V. For applications where it is more appropriate to have SD
(Vsd) connected to Vdd, an 18k Ohms resistor value for R2 is suggested (where Vdd = 2.85V).
For low-voltage operation such as Vdd = 1.5V or 1.0V, R2 may be omitted and SD (Vsd) connected directly to Vdd.
The grounding regime for the ALM-2412 is critical to achieving the PCS- and Cell-Band Rejections shown in Figure 9. Please refer to the PCB Land
Patterns section of this document for the exact locations of the grounding vias.
5
5 Page 
ALM-2412 Typical Noise Parameter at 25°C,
Freq = 1.575GHz, Vdd = 2.85V, Idd = 9mA
Freq Fmin GAMMA OPT
(GHz)
(dB)
Mag
Ang
1.575
0.7
0.55 62
Rn/50
0.36
Part Number Ordering Information
Part Number
No. of Devices
ALM-2412-BLKG
100
ALM-2412-TR1G
3000
Container
Antistatic Bag
13” Reel
Notes:
The exceptional noise figure performance of the ALM-2412 is due to its highly optimized design. In this regard, the Fmin of the ALM-2412 shown
above is locked down by the internal input pre-match. This allows the use of relatively inexpensive chip inductors for external matching.
The NF performance of the ALM-2412 is also very resilient to operating conditions. For example, at Idd = 5mA, the degradation in NF is only 0.1dB,
and not more than 0.15dB degradation over temperature.
Package Dimensions
PIN 1 ORIENTATION
2x–0.69
0.50
0.10
ALL EDGES
0.10 0.07
GAPS
2x–0.28
2412
XXXXX
2.10 ±0.10
5x–0.35 SQ
2x–0.47
3.30 ± 0.10
TOP VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONS ARE INCLUSIVE OF PLATING.
3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR.
1.10 ± 0.10
SIDE VIEW
PCB Land Patterns and Stencil Design
2x–0.28
0.60 1.55
2x–1.76
2x–0.20
7x–0.16
BOTTOM VIEW
PCB Land Pattern and Suggested Grounding Vias
Dimensions are in mm
11
Stencil Outline Drawing
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ALM-2412.PDF ] | |
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