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Número de pieza | AS6WA25616 | |
Descripción | 3.0V to 3.6V 256K X 16 Intelliwat low-power CMOS SRAM | |
Fabricantes | Alliance Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AS6WA25616 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
No Preview Available ! September 2001
AS6WA25616
3.0V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable
Features
• AS6WA25616
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words × 16 bits
• 3.0V to 3.6V at 55 ns
• Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
• Low power consumption: STANDBY
- 72 µW max at 3.6V
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
I/O
buffer
256K × 16
Array
(4,194,304)
VCC
VSS
Control circuit
WE Column decoder
UB
OE
LB
CS
• 1.5V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement (top view)
44-pin 400-mil TSOP 2
A4
A3
A2
A1
A0
CS
I/O1
I/O2
I/O3
I/O4
I/VVOCS5CS
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VVI/SCOSC12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
48-CSP Ball-Grid-Array Package
123456
A LB OE A0 A1 A2 NC
B I/O9 UB A3 A4 CS I/O1
C I/O10 I/O11 A5 A6 I/O2 I/O3
D VSS I/O12 A17 A7 I/O4 VCC
E VCC I/O13 NC A16 I/O5 VSS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
H NC A8 A9 A10 A11 NC
Selection guide
Product
AS6WA25616
Min
(V)
3.0
VCC Range
Typ2
(V)
3.3
Max
(V)
3.6
Speed
(ns)
55
Power Dissipation
Operating (ICC)
Max (mA)
Standby (ISB1)
Max (µA)
2 20
7/9/02; v.1.3
Alliance Semiconductor
P. 1 of 9
Copyright ©Alliance Semiconductor. All rights reserved.
1 page AS6WA25616
Write cycle (over the operating range).
Parameter
Write cycle time
Chip select to write end
Address setup to write end
Address setup time
Write pulse width
Write recovery time
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
UB/LB low to end of write
Symbol
tWC
tCW
tAW
tAS
tWP
tWR
tAH
tDW
tDH
tWZ
tOW
tBW
Min
55
40
40
0
35
0
0
25
0
0
5
35
Max Unit
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
20 ns
– ns
– ns
Write waveform 1 (WE controlled)
Address
CS
LB, UB
WE
tAS
tWC
tCW
tBW
tAW
DIN
DOUT
Data undefined
tWZ
tWR
tAH
tWP
tDW tDH
Data valid
tOW
High Z
Notes
12
12
4, 5
4, 5
4, 5
Write waveform 2 (CS controlled)
Address
CS
tAS
LB, UB
WE
DIN
DOUT
tCLZ
High Z
tWC tWR
tCW tAH
tAW
tBW
tWP
tWZ
Data undefined
tDW tDH
Data valid
tOW
High Z
7/9/02; v.1.3
Alliance Semiconductor
P. 5 of 9
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet AS6WA25616.PDF ] |
Número de pieza | Descripción | Fabricantes |
AS6WA25616 | 3.0V to 3.6V 256K X 16 Intelliwat low-power CMOS SRAM | Alliance Semiconductor |
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