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PDF PI7C7300D Data sheet ( Hoja de datos )
| Número de pieza | PI7C7300D | |
| Descripción | 3-PORT PCI-to-PCI BRIDGE | |
| Fabricantes | Pericom Semiconductor Corporation | |
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PI7C7300D
3-PORT PCI-to-PCI BRIDGE
Revision 1.01
3545 North 1ST Street, San Jose, CA 95134
Telephone: 1-877-PERICOM (1-877-737-4266)
FAX: 408-435-1100
Internet: http://www.pericom.com
1 page  
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
TABLE OF CONTENTS
1 INTRODUCTION ............................................................................................................................ 11
2 BLOCK DIAGRAM......................................................................................................................... 12
3 SIGNAL DEFINITIONS ................................................................................................................. 13
3.1 SIGNAL TYPES ........................................................................................................................ 13
3.2 PRIMARY BUS INTERFACE SIGNALS ................................................................................ 13
3.3 SECONDARY BUS INTERFACE SIGNALS .......................................................................... 15
3.4 CLOCK SIGNALS..................................................................................................................... 17
3.5 MISCELLANEOUS SIGNALS ................................................................................................. 17
3.6 COMPACT PCI HOT-SWAP SIGNALS .................................................................................. 17
3.7 JTAG BOUNDARY SCAN SIGNALS ..................................................................................... 18
3.8 POWER AND GROUND .......................................................................................................... 18
3.9 PI7C7300D PBGA PIN LIST .................................................................................................... 18
4 PCI BUS OPERATION ................................................................................................................... 21
4.1 TYPES OF TRANSACTIONS .................................................................................................. 21
4.2 SINGLE ADDRESS PHASE ..................................................................................................... 22
4.3 DUAL ADDRESS PHASE ........................................................................................................ 22
4.4 DEVICE SELECT (DEVSEL#) GENERATION ...................................................................... 23
4.5 DATA PHASE ........................................................................................................................... 23
4.6 WRITE TRANSACTIONS ........................................................................................................ 23
4.6.1 MEMORY WRITE TRANSACTIONS.................................................................................. 24
4.6.2 MEMORY WRITE AND INVALIDATE TRANSACTIONS.................................................. 25
4.6.3 DELAYED WRITE TRANSACTIONS ................................................................................. 25
4.6.4 WRITE TRANSACTION ADDRESS BOUNDARIES .......................................................... 26
4.6.5 BUFFERING MULTIPLE WRITE TRANSACTIONS......................................................... 26
4.6.6 FAST BACK-TO-BACK WRITE TRANSACTIONS ............................................................ 27
4.7 READ TRANSACTIONS.......................................................................................................... 27
4.7.1 PREFETCHABLE READ TRANSACTIONS....................................................................... 27
4.7.2 NON-PREFETCHABLE READ TRANSACTIONS ............................................................. 27
4.7.3 READ PREFETCH ADDRESS BOUNDARIES.................................................................. 28
4.7.4 DELAYED READ REQUESTS ........................................................................................... 30
4.7.5 DELAYED READ COMPLETION WITH TARGET ........................................................... 30
4.7.6 DELAYED READ COMPLETION ON INITIATOR BUS................................................... 32
4.7.7 FAST BACK-TO-BACK READ TRANSACTION................................................................ 32
4.8 CONFIGURATION TRANSACTIONS.................................................................................... 33
4.8.1 TYPE 0 ACCESS TO PI7C7300D ...................................................................................... 33
4.8.2 TYPE 1 TO TYPE 0 CONVERSION ................................................................................... 34
4.8.3 TYPE 1 TO TYPE 1 FORWARDING.................................................................................. 35
4.8.4 SPECIAL CYCLES ............................................................................................................. 36
4.9 TRANSACTION TERMINATION ........................................................................................... 37
4.9.1 MASTER TERMINATION INITIATED BY PI7C7300D..................................................... 37
4.9.2 MASTER ABORT RECEIVED BY PI7C7300D.................................................................. 38
4.9.3 TARGET TERMINATION RECEIVED BY PI7C7300D..................................................... 38
4.9.4 TARGET TERMINATION INITIATED BY PI7C7300D..................................................... 41
4.10 CONCURRENT MODE OPERATION..................................................................................... 42
5 ADDRESS DECODING .................................................................................................................. 42
Pericom Semiconductor
Page 5 of 107
November 2005 - Revision 1.01
5 Page 
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
1 INTRODUCTION
PRODUCT DESCRIPTION
The PI7C7300D is Pericom Semiconductor’s second-generation PCI-PCI Bridge and is
an updated revision to the PI7C7300A. It is designed to be fully compliant with the 32-
bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The
PI7C7300D supports only synchronous bus transactions between devices on the Primary
Bus running at 33MHz to 66MHz and the Secondary Buses operating at either 33MHz or
66MHz. The Primary and Secondary Buses can also operate in concurrent mode,
resulting in added increase in system performance. Concurrent bus operation off-loads
and isolates unnecessary traffic from the Primary Bus; thereby enabling a master and a
target device on the same Secondary PCI Bus to communicate even while the Primary
Bus is busy. In addition, the Secondary Buses have load balancing capability, allowing
faster devices to be isolated away from slower devices. Among the other features
supported by the PI7C7300D are: support for up to 15 devices on the Secondary Buses,
Compact PCI Hot Swap (PICMG 2.1, R1.0) Friendly Support and Dual Addressing
Cycle.
PRODUCT FEATURES
• 32-bit Primary and Two Secondary Ports run up to 66MHz
• All 3 ports compliant with the PCI Local Bus Specification, Revision 2.2
• Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1.
- All I/O and memory commands
- Type 1 to Type 0 configuration conversion
- Type 1 to Type 1 configuration forwarding
- Type 1 configuration write to special cycle conversion
• Concurrent Primary to Secondary Bus operation and independent intra-Secondary
Port channel to reduce traffic on the Primary Port
• Provides internal arbitration for one set of eight secondary bus masters (S1 bus) and
one set of seven (eight if Hot Swap is disabled) secondary bus masters (S2 bus)
- Programmable 2-level priority arbiter
- Disable control for use of external arbiter
• Supports posted write buffers in all directions
• Three 128 byte FIFO’s for delay transactions
• Three 128 byte FIFO’s for posted memory transactions
• Enhanced address decoding
- 32-bit I/O address range
- 32-bit memory-mapped I/O address range
- VGA addressing and VGA palette snooping
- ISA-aware mode for legacy support in the first 64KB of I/O address range
• Dual Addressing cycle (64-bit)
• Supports system transaction ordering rules
• Tri-state control of output buffers on secondary buses
• Compact PCI Hot Swap (PICMG 2.1, R1.0) Friendly Support
• Industrial Temperature range –40°C to 85°C
• IEEE 1149.1 JTAG interface support
• 3.3V core; 3.3V PCI I/O interface with 5V I/O tolerance
• 272-pin plastic BGA package
Pericom Semiconductor
Page 11 of 107
November 2005 - Revision 1.01
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet PI7C7300D.PDF ] | |
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