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PDF EN6347QA Data sheet ( Hoja de datos )
| Número de pieza | EN6347QA | |
| Descripción | 4A PowerSoC Voltage Mode Synchronous PWM Buck | |
| Fabricantes | Altera | |
| Logotipo |  |
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Enpirion® Power Datasheet
EN6347QA 4A PowerSoC
Voltage Mode Synchronous
PWM Buck with Integrated Inductor
Description
The EN6347QA is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal circuits, compensation, and the
inductor in an advanced 4mm x 7mm x 1.85mm 38-
pin QFN package.
The EN6347QA is specifically designed to meet the
precise voltage and fast transient requirements of
present and future high-performance, low-power
processor, DSP, FPGA, memory boards and system
level applications in distributed power architecture.
The device’s advanced circuit techniques, ultra high
switching frequency, and proprietary integrated
inductor technology deliver high-quality, ultra
compact, non-isolated DC-DC conversion.
The Altera Enpirion power solution significantly helps
in system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, a reduction in the number
of vendors required for the complete power solution
helps to enable an overall system cost savings.
All Enpirion products are RoHS compliant and lead-
free manufacturing environment compatible.
Features
• Integrated Inductor, MOSFETs, Controller
• Up to 4A Continuous Operating Current
• High Efficiency (Up to 95%)
• Frequency Synchronization to External Clock
• Input Voltage Range (2.5V to 6.6V)
• Programmable Light Load Mode
• Optimized Total Solution Size (90mm2)
• Output Enable Pin and Power OK
• Programmable Soft-Start
• Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltage Protection
• RoHS Compliant, MSL Level 3, 260°C Reflow
Applications
• Automotive Applications
• Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
• Blade Servers, RAID Storage and LAN/SAN
Adapter Cards, Wireless Base Stations, Industrial
Automation, Test and Measurement, Embedded
Computing, and Printers
• High Efficiency 12V Intermediate Bus Architectures
• Beat Frequency/Noise Sensitive Applications
VIN
560Ω
22µF
1206
X7R
CSS
EN6347QA
PVIN
AVIN
PG
VOUT
VFB
PGND PGND
SS LLM/
AGND SYNC
RA
CA
RB
Figure 1. Simplified Applications Circuit
VOUT
47µF
1210
X7R
Efficiency vs. Output Current
100
90
80
70
60
50
40
CONDITIONS
90mm2
30 VIN = 5V
20
VOUT = 3.3V LLM
EN6347QA
4 mm x 7 mm
10
0
0.01
VOUT = 3.3V PWM
0.1 1
OUTPUT CURRENT (A)
10
Figure 2. Highest Efficiency in Smallest Solution Size
10318
October 1, 2014
www.altera.com/enpirion
Rev A
1 page  
EN6347QA
PARAMETER
Over Current Trip
Level
Disable Threshold
ENABLE Threshold
ENABLE Lockout Time
ENABLE pin Input
Current (Note 3)
Switching Frequency
(Free Running)
External SYNC Clock
Frequency Lock
Range
SYNC Input Threshold
– Low (LLM/SYNC
PIN)
SYNC Input Threshold
– High (LLM/SYNC
PIN)
(Note 5)
POK Lower Threshold
POK Output low
Voltage
POK Output Hi Voltage
POK pin VOH leakage
current (Note 3)
SYMBOL
IOCP
VDISABLE
VENABLE
TENLOCKOUT
IENABLE
FSW
FPLL_LOCK
VSYNC_LO
VSYNC_HI
POKLT
VPOKL
VPOKH
IPOKL
TEST CONDITIONS
VIN = 5V, VOUT = 1.2V
ENABLE pin logic low.
ENABLE pin logic high
2.5V ≤ VIN ≤ 6.6V
ENABLE pin has ~180kΩ pull down
Free Running frequency of
oscillator
Range of SYNC clock frequency
SYNC Clock Logic Level
SYNC Clock Logic Level
Output voltage as a fraction of
expected output voltage
With 4mA current sink into POK
2.5V ≤ VIN ≤ 6.6V
POK high
MIN
0.0
1.8
2.5
1.8
TYP
5
3.2
40
3
90
MAX
0.6
VIN
3.5
0.8
2.5
0.4
VIN
1
UNITS
A
V
V
ms
µA
MHz
MHz
V
V
%
V
V
µA
LLM Engage
Headroom
Minimum VIN-VOUT to ensure proper
LLM operation
800
mV
LLM Logic Low
(LLM/SYNC PIN)
VLLM_LO
LLM Static Logic Level
0.3 V
LLM Logic High
(LLM/SYNC PIN)
VLLM_HI
LLM Static Logic Level
1.5
V
LLM/SYNC Pin
Current
LLM/SYNC Pin is <2.5V
<100
nA
Note 3: Parameter not production tested but is guaranteed by design.
Note 4: LLM operation is normally only guaranteed above the minimum specified output current. Contact Power
Applications support for designs that need to operate at a lower IOUT.
Note 5: For proper operation of the synchronization circuit, the high-level amplitude of the SYNC signal should not be
above 2.5V.
Note 6: The VFB pin is a sensitive node. Do not touch VFB while the device is in regulation.
10318
October 1, 2014
www.altera.com/enpirion, Page 5
Rev A
5 Page 
Typical Performance Characteristics (Continued)
EN6347QA
Enable Power Up/Down
ENABLE
Enable Power Up/Down
ENABLE
VOUT
POK
LOAD
CONDITIONS
VIN = 5.5V, VOUT = 3.3V
NO LOAD, Css = 47nF
CIN = 22µF (1206)
COUT = 47 µF (1210)
LLM Load Transient from 0.01 to 4A
VOUT
(AC Coupled)
VOUT
POK
LOAD
CONDITIONS
VIN = 5.0V, VOUT = 3.3V, LOAD=0.825Ω, Css = 47nF
CIN = 22µF (1206), COUT = 47 µF (1210)
LLM Load Transient from 0.01 to 4A
VOUT
(AC Coupled)
LOAD
CONDITIONS
LLM = ENABLED
VIN = 5V
VOUT = 1V
CIN = 22µF (1206)
COUT = 2 x 47µF (1210)
PWM Load Transient from 0 to 4A
VOUT
(AC Coupled)
LOAD
CONDITIONS
LLM = ENABLED
VIN = 5V
VOUT = 3V
CIN = 22µF (1206)
COUT = 2 x 47µF (1210)
PWM Load Transient from 0 to 4A
VOUT
(AC Coupled)
LOAD
CONDITIONS
LLM = DISABLED
VIN = 5V
VOUT = 1V
CIN = 22µF (1206)
COUT = 47µF (1210) + 10µF (1206)
LOAD
CONDITIONS
LLM = DISABLED
VIN = 5V
VOUT = 3V
CIN = 22µF (1206)
COUT = 47µF (1210) + 10µF (1206)
10318
October 1, 2014
www.altera.com/enpirion, Page 11
Rev A
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet EN6347QA.PDF ] | |
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