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PDF LTC3240-3.3 Data sheet ( Hoja de datos )

Número de pieza LTC3240-3.3
Descripción 3.3V/2.5V Step-Up/Step-Down Charge Pump DC/DC Converter
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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No Preview Available ! LTC3240-3.3 Hoja de datos, Descripción, Manual

LTC3240-3.3/LTC3240-2.5
3.3V/2.5V Step-Up/
Step-Down Charge Pump
DC/DC Converter
FEATURES
Step-Up/Step-Down Charge Pumps Generate Fixed
3.3V or 2.5V Outputs
VIN Range: 1.8V to 5.5V
Output Current up to 150mA
Automatic Mode Switching
Constant Frequency (1.2MHz) Operation in
Step-Up Mode
Low Dropout Regulator Operation in
Step-Down Mode
Low No-Load Quiescent Current: IQ = 65µA
Built-In Soft-Start Reduces Inrush Current
Shutdown Disconnects Load from Input
Shutdown Current < 1µA
Short-Circuit/Thermal Protection
Available in a 6-Lead (2mm × 2mm) DFN Package
U
APPLICATIO S
2 AA to 2.5V
2-3 AA/Li-Ion to 3.3V
Low Power Supplies for Cameras, I/O Supplies,
Audio, PC Cards, Misc. Logic, etc., in a Wide Variety
of Handheld Products
DESCRIPTIO
The LTC®3240-3.3/LTC3240-2.5 are step-up/step-down
charge pump DC/DC converters that produce a fixed
regulated output voltage of 3.3V or 2.5V over a wide input
voltage range (1.8V to 5.5V).
With input voltages greater than the regulated output
voltage the LTC3240 operates as a low dropout regulator.
Once the input voltage drops within 100mV of the regulated
output voltage the part automatically switches to step-up
mode. In step-up mode the LTC3240 operates as a constant
frequency (1.2MHz) doubling charge pump.
The LTC3240-3.3/LTC3240-2.5 feature low no load operat-
ing current (65µA typical) and ultralow operating current
in shutdown (<1µA). Built-in soft-start circuitry prevents
excessive inrush current during start-up. Thermal shut-
down and current-limit circuitry allow the parts to survive
a continuous short-circuit from VOUT to GND.
The LTC3240-3.3/LTC3240-2.5 require only three tiny
external ceramic capacitors for an ultrasmall application
footprint. The LTC3240-3.3/LTC3240-2.5 are available in a
6-pin (2mm × 2mm) DFN package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6411531.
TYPICAL APPLICATIO
Li-Ion to 3.3V at Up to 150mA
1µF
2.7V TO 4.5V
Li-Ion OR
3-CELL NiMH
1µF
C
VIN
C+
VOUT
LTC3240-3.3
GND
3.3V
IOUT = 150mA
4.7µF
OFF ON
SHDN
3240 TA01a
Output Voltage vs Input Voltage (Full Range)
3.50
IOUT = 30mA
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
1.7 2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7
INPUT VOLTAGE (V)
3240 TA01b
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LTC3240-3.3 pdf
LTC3240-3.3/LTC3240-2.5
TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C, CFLY = CIN = 1µF, COUT = 4.7µF
unless otherwise noted)
Load Transient Response
(LTC3240-3.3)
Output Noise/Ripple
(LTC3240-2.5)
Load Transient Response
(LTC3240-2.5)
VOUT
20mV/DIV
AC COUPLED
LDO MODE
60mA
ILOAD
10mA
VIN = 3.7V
10µs/DIV
ILOAD = 10mA TO 60mA
VOUT
20mV/DIV
AC COUPLED
3240 G15
VIN = 2.4V
500ns/DIV
ILOAD = 100mA
VOUT
20mV/DIV
AC COUPLED
Burst Mode
OPERATION
CONST FREQUENCY
MODE
50mA
ILOAD
10mA
3240 G16
VIN = 2.4V
10µs/DIV
ILOAD = 10mA TO 50mA
3240 G17
PI FU CTIO S
GND (Pin 1): Ground. This pin should be tied to a ground
plane for best performance.
VIN (Pin 2): Input Supply Voltage. VIN should be bypassed
with a 1μF or greater, low ESR ceramic capacitor.
VOUT (Pin 3): Regulated Output Voltage. VOUT should be
bypassed with a 4.7μF or greater, low ESR ceramic capaci-
tor as close to the pin as possible for best performance.
C+ (Pin 4): Flying Capacitor Positive Terminal.
C(Pin 5): Flying Capacitor Negative Terminal.
SHDN(Pin 6): Active Low Shutdown Input. A low on SHDN
disables the LTC3240-3.3/LTC3240-2.5. This pin is a high
impedance CMOS input pin which must be driven with valid
logic levels. This pin must not be allowed to float.
Exposed Pad (Pin 7): Ground. The exposed pad must be
soldered to PCB ground to provide electrical contact and
optimum thermal performance.
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LTC3240-3.3 arduino
APPLICATIO S I FOR ATIO
3.0
θJA = 80°C/W
2.5
2.0
THERMAL
SHUTDOWN
1.5 TJ = 160°C
1.0
RECOMMENDED
OPERATION
0.5 TJ = 125°C
0
– 50 – 25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C)
LT3240 F05
Figure 5. Maximum Power Dissipation vs Ambient Temperature
LTC3240-3.3/LTC3240-2.5
This derating curve assumes a maximum thermal resis-
tance, θJA, of 80°C/W for the 2 × 2 DFN package. This can
be achieved from a printed circuit board layout with a solid
ground plane and a good connection to the ground pins of
LTC3240 and the Exposed Pad of the DFN package.
It is recommended that the LTC3240 be operated in the
region corresponding to TJ ≤ 125°C for continuous opera-
tion as shown in Figure 5. Short term operation may be
acceptable for 125°C ≤ TJ ≤ 160°C but long term operation
in this region should be avoided as it may reduce the life of
the part or cause degraded performance. For TJ ≥ 160°C,
the part will be in thermal shutdown.
PACKAGE DESCRIPTIO
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
2.50 ±0.05
1.15
±0.05
0.61 ±0.05
(2 SIDES)
0.675 ±0.05
PACKAGE
OUTLINE
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.25 ± 0.05
0.50 BSC
1.42 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.200 REF
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
R = 0.115
TYP
0.56 ± 0.05
(2 SIDES)
4
0.38 ± 0.05
6
2.00 ±0.10
(4 SIDES)
0.75 ±0.05
0.00 – 0.05
PIN 1
CHAMFER OF
EXPOSED PAD
31
(DC6) DFN 1103
0.25 ± 0.05
0.50 BSC
1.37 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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