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PDF ISL78420 Data sheet ( Hoja de datos )
| Número de pieza | ISL78420 | |
| Descripción | Half-Bridge Driver | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM
Input and Adjustable Dead-Time
ISL78420
The ISL78420 is a 100V, high frequency, half-bridge MOSFET
driver with a tri-level PWM input. This part is a derivative of the
HIP2121 half-bridge driver. The non-automotive version of the
ISL78420 is the HIP2124.
This driver is designed to work in conjunction with the ISL78220,
“6-Phase Interleaved Boost PWM Controller with Light Load
Efficiency Enhancement”. Equally, it can be used in most
applications where a half-bridge driver is used.
This driver has a programmable dead-time to ensure
break-before-make operation between the high-side and low-side
drivers. A resistor is used to adjust the dead-time up to 220ns.
The tri-level input allows the PWM input to also function as a
disable input. When the PWM input is a logic high, the high-side
bridge FET is turned on and the low-side FET is off. When the
input is a logic low, the low-side bridge FET is turned on and the
high-side FET is turned off. When the input voltage is midrange,
both the high and low-side bridge FETs are turned off.
The enable pin (EN), when low, drives both outputs to a low state.
This input is used when the controller does not utilize a tri-state
output. All logic inputs are VDD tolerant.
Two package options are provided. The 10 Ld 4x4 DFN package
has standard pinouts. The 9 Ld 4x4 DFN package omits pin 2 to
comply with 100V conductor spacing per IPC-2221.
Features
• Programmable break-before-make dead-time prevents
shoot-through and is adjustable up to 220ns
• Bootstrap supply maximum voltage to 114VDC
• Wide supply voltage range (8V to 14V)
• Supply undervoltage protection
• On-chip 1Ω bootstrap diode
• Unique tri-level PWM input logic enables phase shedding when
using multi-phase PWM controllers (e.g. ISL78220/225)
• 9 Ld TDFN “B” package compliant with 100V conductor
spacing guidelines per IPC-2221
• AEC Q100 Qualified
Applications
• Automotive applications
• Multi-phase boost (ISL78220/225)
• Half-bridge DC/DC converter
• Class-D amplifiers
• Forward converter with active clamp
Related Literature
• FN7668 HIP2120, HIP2121 “100V, 2A Peak, High Frequency
Half-Bridge Drivers with Adjustable Dead Time Control and
PWM Input”
• FN8363 HIP2124, “100V, 2A Peak, Half Bridge Driver with
Tri-level Input and Adjustable Dead Time” (non-automotive)
• FN7688 ISL78220, “6-Phase Interleaved Boost PWM
Controller with Light Load Efficiency Enhancement”
• FN7909 ISL78225, “4-Phase Interleaved Boost PWM
Controller with Light Load Efficiency Enhancement”
HALF BRIDGE
ISL78420
VDD
HB
PWM
CONTROLLER
PWM
EN
RDT
HO
HS
VSS LO
EPAD
100V MAX
SECONDARY
CIRCUITS
FEEDBACK
WITH
ISOLATION
FIGURE 1. TYPICAL APPLICATION
200
160
140
120
100
80
60
40
20
8 16 24 32 40 48 56 64
RDT (kΩ)
FIGURE 2. DEAD-TIME vs TIMING RESISTOR
80
January 24, 2014
FN8296.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL78420
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0K, PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETERS
SYMBOL
TEST CONDITIONS
TA = +25°C
MIN TYP MAX
TA = -40°C to +125°C
MIN
(Note 9)
MAX
(Note 9)
UNITS
EN Input
Low Level Input Threshold
High Level Input Threshold
EN Pull-up Resistance
UNDERVOLTAGE PROTECTION
VENL
VENH
Rpu
1.4 1.8 -
- 1.8 2.2
- 210 -
1.2
-
100
-V
2.4 V
320 kΩ
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
HB Threshold Hysteresis
BOOTSTRAP DIODE
VDDR
VDDH
VHBR
VHBH
6.8 7.3 7.8
- 0.6 -
6.2 6.9 7.5
- 0.6 -
6.5
-
5.9
-
8.1 V
-V
7.8 V
-V
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
LO GATE DRIVER
VDL IVDD-HB = 100mA
VDH IVDD-HB = 100mA
RD IVDD-HB = 100mA
- 0.6 0.7
- 0.7 0.9
- 0.8 1
-
-
-
0.8 V
1V
1.5 Ω
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
Peak Pull-Down Current
HO GATE DRIVER
VOLL
VOHL
IOHL
IOLL
ILO = 100mA
ILO = -100mA, VOHL = VDD - VLO
VLO = 0V
VLO = 12V
- 0.25 0.4
- 0.25 0.4
-2-
-2-
-
-
-
-
0.5 V
0.5 V
-A
-A
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
Peak Pull-Down Current
VOLH
VOHH
IOHH
IOLH
IHO = 100mA
IHO = -100mA, VOHH = VHB - VHO
VHO = 0V
VHO = 12V
- 0.25 0.4
- 0.25 0.4
-2-
-2-
-
-
-
-
0.5 V
0.5 V
-A
-A
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0kΩ, No Load on LO or HO, Unless Otherwise Specified. Boldface
limits apply over the operating temperature range, -40°C to +125°C.
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = +25°C
MIN TYPE MAX
TJ = -40°C to +125°C
MIN
(Note 9)
MAX
(Note 9)
UNITS
HO Turn-Off Propagation Delay
PWM Falling to HO Falling
tPLHO
- 32 50
-
60 ns
LO Turn-Off Propagation Delay
PWM Rising to LO Falling
tPLLO
- 32 50
-
60 ns
Minimum Dead-Time Delay (Note 10)
HO Falling to LO Rising
tDTHLmin RDT = 80k,
PWM 1 to 0
15 35 50
10
60 ns
Minimum Dead-Time Delay (Note 10)
LO Falling to HO Rising
tDTLHmin RDT = 80k
PWM 0 to 1
15 25 50
10
60 ns
Maximum Dead-Time Delay (Note 10)
HO Falling to LO Rising
tDTHLmax RDT = 8k,
PWM 1 to 0
150 220 300
-
- ns
5 FN8296.2
January 24, 2014
5 Page 
ISL78420
8V TO 15V
VDD
HB
100V MAX
PWM*
PWM
CONTROLLER
PWM
EN
RDT
HI HO
DRIVER
HS
LO LO
DRIVER
ISL78420
VSS
FIGURE 19. TYPICAL ACTIVE CLAMP FORWARD APPLICATION
Typical Application Circuit
Figure 19 is an example of how the ISL78420 can be configured
for an active clamp forward power supply application. Note that
the PWM signal from the controller must be inverted for this
active clamp forward topology.
Depending on the application, the switching speed of the bridge
FETs can be reduced by adding series connected resistors
between the xHO outputs and the FET gates. Gate-Source
resistors are recommended on the low-side FETs to prevent
unexpected turn-on of the bridge should the bridge voltage be
applied before VDD. Gate-source resistors on the high-side FETs
are not usually required if low-side gate-source resistors are
used. If relatively low value gate-source resistors are used on the
high-side FETs, be aware that a larger value for the boot capacitor
may be required.
Transients on HS Node
An important operating condition that is frequently overlooked by
designers is the negative transient on the xHS pins that occurs
when the high-side bridge FET turns off. The Absolute Maximum
transient allowed on the xHS pin is -6V but it is wise to minimize
the amplitude to lower levels. This transient is the result of the
parasitic inductance of the low-side drain-source conductor on
the PCB. Even the parasitic inductance of the low-side FET
contributes to this transient.
When the high-side bridge FET turns off (see Figure 20), because
of the inductive characteristics the load, the current that was
flowing in the high-side FET (blue) must rapidly commutate to
flow through the low-side FET (red). The amplitude of the
negative transient impressed on the xHS node is (di/dt x L) where
L is the total parasitic inductance of the low-side FET
drain-source path and di/dt is the rate at which the high-side FET
is turned off. With the increasing power levels of power supplies
and motors, clamping this transient become more and more
significant for the proper operation of the ISL78420.
HB
H O IN D U C T IV E
LOAD
HS
LO
VSS
-
+
-
+
FIGURE 20. PARASITIC INDUCTANCE CAUSES TRANSIENTS ON HS
NODE
There are several ways of reducing the amplitude of this
transient. If the bridge FETs are turned off more slowly to reduce
di/dt, the amplitude will be reduced but at the expense of more
switching losses in the FETs. Careful PCB design will also reduce
the value of the parasitic inductance. However, these two
solutions by themselves may not be sufficient. Figure 20
illustrates a simple method for clamping the negative transient.
A fast PN junction, 1A diode is connected between xHS and VSS
as shown. It is important that this diode be placed as close as
possible to the xHS and VSS pins to minimize the parasitic
inductance of this current path. Because this clamping diode is
essentially in parallel with the body diode of the low-side FET, a
small value resistor is necessary to limit current when the body
diode of the low-side bridge FET is conducting during the dead
time. The resistor in series with HS, can be used instead of the
gate resistor of the high-side FET.
Please note that a similar transient with a positive polarity occurs
when the low-side FET turns off. This is less frequently a problem
because xHS node is floating up toward the bridge bias voltage.
The Absolute Max voltage rating for the xHS node does need to
be observed when the positive transient occurs.
11 FN8296.2
January 24, 2014
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL78420.PDF ] | |
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