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PDF MX25V4035 Data sheet ( Hoja de datos )
| Número de pieza | MX25V4035 | |
| Descripción | FLASH MEMORY | |
| Fabricantes | Macronix International | |
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MX25V4035
MX25V8035
MX25V4035/MX25V8035
DATASHEET
P/N: PM1468
REV. 1.2, JUL. 23, 2010
1
1 page  
MX25V4035
MX25V8035
FEATURES
4M-BIT [x 1/x 2/x 4] 2.5V CMOS SERIAL FLASH
8M-BIT [x 1/x 2/x 4] 2.5V CMOS SERIAL FLASH
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 4M: 4,194,304 x 1 bit structure or 2,097,152 x 2 bits (two I/O read mode) structure or 1,048,576 x 4 bits (four I/
O read mode) structure
8M: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two I/O read mode) structure or 2,097,152 x 4 bits (four I/
O read mode) structure
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.25 to 2.75 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 66MHz with 8 dummy cycles
- 2 I/O: 50MHz with 4 dummy cycles, equivalent to 100MHz
- 4 I/O: 50MHz with 6 dummy cycles, equivalent to 200MHz
- Fast program time: 1.7ms(typ.) and 6ms(max.)/page (256-byte per page)
- Byte program time: 15us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 80ms (typ.)/sector (4K-byte per sector); 0.6s(typ.) /block (32K-byte per block); 1s(typ.) /block
(64K-byte per block); 7.5s(typ.) /chip for 4M; 13s(typ.) /chip for 8M
• Low Power Consumption
- Low active read current: 12mA(max.) at 66MHz, 6mA(max.) at 40MHz
- Low active erase/programming current: 15mA (typ.)
- Low standby current: 7uA (max.)
• Deep Power Down: 7uA(max.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instruc-
tions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector or block
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
P/N: PM1468
REV. 1.2, JUL. 23, 2010
5
5 Page 
MX25V4035
MX25V8035
Table 2. Protected Area Sizes
Status bit
BP3 BP2 BP1 BP0
4Mb
0 0 0 0 0 (none)
0 0 0 1 1 (1block, 1/8 area, block#7)
0 0 1 0 2 (2blocks, 1/4 area, block#6-7)
0 0 1 1 3 (4blocks, 1/2 area, block#4-7)
0 1 0 0 4 (8blocks, ALL)
0 1 0 1 5 (8blocks, ALL)
0 1 1 0 6 (8blocks, ALL)
0 1 1 1 7 (8blocks, ALL)
1 0 0 0 8 (none)
1 0 0 1 9 (1block, 1/8 area, block#0)
1 0 1 0 10 (2blocks, 1/4 area, block#0-1)
1 0 1 1 11 (4blocks, 1/2 area, block#0-3)
1 1 0 0 12 (8blocks, ALL)
1 1 0 1 13 (8blocks, ALL)
1 1 1 0 14 (8blocks, ALL)
1 1 1 1 15 (8blocks, ALL)
Protect Level
8Mb
0 (none)
1 (1block, 1/16 area, block#15)
2 (2blocks, 1/8 area, block#14-15)
3 (4blocks, 1/4 area, block#12-15)
4 (8blocks, 1/2 area, block#8-15)
5 (16blocks, ALL)
6 (16blocks, ALL)
7 (16blocks, ALL)
8 (none)
9 (1block, 1/16 area, block#0)
10 (2blocks, 1/8 area, block#0-1)
11 (4blocks, 1/4 area, block#0-3)
12 (8blocks, 1/2 area, block#0-7)
13 (16blocks, ALL)
14 (16blocks, ALL)
15 (16blocks, ALL)
II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting
device unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512-bit
secured OTP definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and go-
ing through normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR (write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security
register bit definition and table of "512-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit se-
cured OTP mode, array access is not allowed.
Table 3. 512-bit Secured OTP Definition
Address range
xxxx00~xxxx0F
xxxx10~xxxx3F
Size
128-bit
384-bit
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
Determined by customer
P/N: PM1468
REV. 1.2, JUL. 23, 2010
11
11 Page | ||
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| PDF Descargar | [ Datasheet MX25V4035.PDF ] | |
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