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PDF MX29F1611 Data sheet ( Hoja de datos )
| Número de pieza | MX29F1611 | |
| Descripción | 16M-BIT [2M x 8/1M x 16] CMOS SINGLE VOLTAGE PAGEMODE FLASH EEPROM | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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INDEX
PRELIMINARY
MX29F1611
FEATURES
16M-BIT [2M x 8/1M x 16] CMOS
SINGLE VOLTAGE PAGEMODE FLASH EEPROM
• 5V ± 5% write, erase and read
• JEDEC-standard EEPROM commands
• Endurance: 10,000 cycles
• Fast access time: 100/120/150ns
• Fast pagemode access time: 50/60/70ns
• Page access depth: 16 bytes/8 words, page address
A0, A1, A2
• Sector erase architecture
- 16 equal sectors of 128k bytes each
- Sector erase time: 150ms typical
• Auto Erase and Auto Program Algorithms
- Automatically erases any one of the sectors or the
whole chip with Erase Suspend capability
- Automatically programs and verifies data at
specified addresses
• Status Register feature for detection of program or
erase cycle completion
• Low VCC write inhibit is equal to or less than 3.2V
• Software and hardware data protection
• Page program operation
- Internal address and data latches for 128 bytes/64
words per page
- Page programming time: 5ms typical
- Byte programming time: 39us in average
• Low power dissipation
- 80mA active current
- 100uA standby current
• CMOS inputs and outputs
• Two independently Protected sectors
• Industry standard surface mount packaging
- 44 lead SOP
GENERAL DESCRIPTION
The MX29F1611 is a 16-mega bit Pagemode Flash
memory organized as either 1M wordx16 or 2M bytex8.
The MX29F1611 includes 16-128KB(131,072 Bytes)
blocks or 16-64KW(65,536 Words)blocks. MXIC's Flash
memories offer the most cost-effective and reliable read/
write non-volatile random access memory and fast page
mode access. The MX29F1611 is packaged 44-pin
SOP. It is designed to be reprogrammed and erased in-
system or in-standard EPROM programmers.
The standard MX29F1611 offers access times as fast as
100ns,allowing operation of high-speed microprocessors
without wait. To eliminate bus contention, the
MX29F1611 has separate chip enable CE, output enable
(OE), and write enable (WE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F1611 uses a command register to manage this
functionality.
To allow for simple in-system reprogrammability, the
MX29F1611 does not require high input voltages for
programming. Five-volt-only commands determine the
operation of the device. Reading data out of the device
is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 10,000 cycles. The MXIC's cell is designed to
optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29F1611 uses a 5V ± 5% VCC supply to perform the
Auto Erase and Auto Program algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
P/N: PM0440
1 REV. 1.6, JUL. 16, 1998
1 page  
INDEX
MX29F1611
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)
Mode
Notes CE OE WE A0 A1 A9
Q0-Q7
Q8-Q14
Q15/A-1
Read
1
VIL VIL VIH
X
X
X
DOUT
DOUT
DOUT
OutputDisable
1
VIL VIH VIH
X
X
X
HighZ
HighZ
HighZ
Standby
1 VIH X X
XXX
HighZ
HIghZ
HighZ
DeepPower-Down 1 X X X X X X
HighZ
HighZ
HighZ
ManufacturerID 2,4 VIL VIL VIH VIL VIL VID
C2H
00H
0B
DeviceID
2,4 VIL VIL VIH VIH VIL VID
F7H
00H
0B
Write
1,3 VIL VIH VIL X X X
DIN
DIN
DIN
Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)
Mode
Notes CE OE WE A0 A1 A9
Q0-Q7
Read
1
VIL VIL VIH
X
X
X
DOUT
OutputDisable
1
VIL VIH VIH
X
X
X
HighZ
Standby
1 VIH X X
XXX
HighZ
DeepPower-Down 1 X X X X X X
HighZ
ManufacturerID 2,4 VIL VIL VIH VIL VIL VID
C2H
DeviceID
2,4 VIL VIL VIH VIH VIL VID
F7H
Write
1,3 VIL VIH VIL X X X
DIN
Q8-Q14
DOUT
HighZ
HIghZ
HighZ
HighZ
HighZ
HighZ
Q15/A-1
VIL/VIH
X
X
X
VIL
VIL
VIL/VIH
NOTES :
1.X can be VIH or VIL for address or control pins.
2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate
sector addresses provide Sector Protect Code.(Refer to Table 4)
3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through
proper command sequence.
4. VID = 11.5V- 12.5V.
5. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.
P/N: PM0440
REV. 1.6, JUL. 16, 1998
5
5 Page 
INDEX
MX29F1611
READ STATUS REGISTER
The MXIC's16 Mbit flash family contains a status register
which may be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The status register may be read
at any time by writing the Read Status command to the
CIR. After writing this command, all subsequent read
operations output data from the status register until
another valid command sequence is written to the CIR. A
Read Array command must be written to the CIR to return
to the Read Array mode.
The status register bits are output on DQ2 - DQ7(table 6)
whether the device is in the byte-wide (x8) or word-wide
(x16) mode for the MX29F1611. In the word-wide mode
the upper byte, DQ(8:15) is set to 00H during a Read
Status command. In the byte-wide mode, DQ(8:14) are
tri-stated and DQ15/A-1 retains the low order address
function. DQ0-DQ1 is set to 0H in either x8 or x16 mode.
It should be noted that the contents of the status register
are latched on the falling edge of OE or CE whichever
occurs last in the read cycle. This prevents possible bus
errors which might occur if the contents of the status
register change while reading the status register. CE or
OE must be toggled with each subsequent status read, or
the completion of a program or erase operation will not be
evident.
The Status Register is the interface between the
microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate the
status of the WSM, and will also hold the bits indicating
whether or not the WSM was successful in performing the
desired operation. The WSM sets status bits four through
seven and clears bits six and seven, but cannot clear
status bits four and five. If Erase fail or Program fail status
bit is detected, the Status Register is not cleared until the
Clear Status Register command is written. The
MX29F1611 automatically outputs Status Register data
when read after Chip Erase, Sector Erase, Page Program
or Read Status Command write cycle. The default state
of the Status Register after powerup and return from deep
power-down mode is (DQ7, DQ6, DQ5, DQ4) = 1000B.
DQ3 = 0 or 1 depends on sector-protect status, can not be
changed by Clear Status Register Command or Write
State Machine. DQ2 = 0 or 1 depends on Sleep status,
During Sleep mode or Abort mode DQ2 is set to "1"; DQ2
is reset to "0" by Read Array command.
CLEAR STATUS REGISTER
The Eraes fail status bit (DQ5) and Program fail status bit
(DQ4) are set by the write state machine, and can only be
reset by the system software. These bits can indicate
various failure conditions(see Table 6). By allowing the
system software to control the resetting of these bits,
several operations may be performed (such as
cumulatively programming several pages or erasing
multiple blocks in squence). The status register may then
be read to determine if an error occurred during that
programming or erasure series. This adds flexibility to the
way the device may be programmed or erased.
Additionally, once the program(erase) fail bit happens,
the program (erase) operation can not be performed
further. The program(erase) fail bit must be reset by
system software before further page program or sector
(chip) erase are attempted. To clear the status register,
the Clear Status Register command is written to the CIR.
Then, any other command may be issued to the CIR.
Note again that before a read cycle can be initiated, a
Read command must be written to the CIR to specify
whether the read data is to come from the Array, Status
Register or Silicon ID.
P/N: PM0440
REV. 1.6, JUL. 16, 1998
11
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet MX29F1611.PDF ] | |
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