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Número de pieza | NL128102BC29-01 | |
Descripción | TFT COLOR LCD MODULE | |
Fabricantes | NEC | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de NL128102BC29-01 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
No Preview Available ! TFT COLOR LCD MODULE
NL128102BC29-01
48.0 cm (19.0 Type)
SXGA
LVDS interface (2port)
PRELIMINARY DATA SHEET
DOD-PD-0410 (2nd edition)
This PRELIMINARY DATA SHEET is updated
document from DOD-PD-0104(1).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PD-0410 (2nd edition) 1 NEC LCD Technologies, Ltd.
Published date: February 2004 CP(N)
2003, 2004 All rights reserved.
1 page NL128102BC29-01
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
Response time
Luminance
Signal system
Power supply voltage
Backlight
Power consumption
376.32 (H) × 301.056 (V) mm (typ.)
48.0 cm (19.0 inches)
a-Si TFT active matrix
16,777,216 colors
1,280 (H) × 1,024 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.098 (H) × 0.294 (V) mm
0.294 (H) × 0.294 (V) mm
404.2 (W) × 330.0 (H) × 22.0 (D) mm (typ.)
2,900 g (typ.)
450:1 (typ.)
At the contrast ratio ≥10:1
• Horizontal: Right side 85° (typ.), Left side 85° (typ.)
• Vertical: Up side 85° (typ.), Down side 85° (typ.)
Viewing angle with optimum grayscale (γ=2.2): normal axis
Antiglare
2H (min.) [by JIS K5400]
At LCD panel center
72 % (typ.) [against NTSC color space]
Ton+Toff (10%←→ 90%)
(25) ms (typ.)
At IBL=6.0mArms / lamp
(300) cd/m2 (typ.)
LVDS 2 port
8bit digital signals for data of RGB colors, Dot clock (CLK),
Data enable (DE)
LCD panel signal processing board: 5.0V
Edge light type: 6 cold cathode fluorescent lamps (without inverter)
At IBL=6.0mArms / lamp and checkered flag pattern
26.8 W (typ., Power dissipation of the inverter does not include.)
2
2
2
2
2
PRELIMINARY DATA SHEET DOD-PD-0410 (2nd edition)
5
5 Page NL128102BC29-01
4.4 POWER SUPPLY VOLTAGE SEQUENCE
2
VDD
Note1, Note4 0V
ON
4.5V
0.1ms < Tr < 80ms
OFF
4.0V 4.5V
20ms max.
Toff > 200ms
Display signals*
TxSEL signal
Note2
0V
VALID period
10 < t < 35ms
10 < t < 35ms
* These signals should be measured at the terminal of 100Ω resistance.
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below (4.5)V, a
protection circuit may work, and then this product may not work.
Note2: Display signals (DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-,
DB3+/-, CKB+/-) and TxSEL signal must be "0" voltage, exclude the VALID period (See
above sequence diagram). If these signals are higher than 0.3V, the internal circuit is damaged.
If some of display and function signals of this product are cut while this product is working,
even if the signal input to it once again, it might not work normally. If customer stops the
display and function signals, they should be cut VDD.
Note3: VDD should be 4.5V or more while VDD ON period.
Note4: The backlight power supply voltage should be inputted within the valid period of display and
function signals, in order to avoid unstable data display.
PRELIMINARY DATA SHEET DOD-PD-0410 (2nd edition)
11
11 Page |
Páginas | Total 27 Páginas | |
PDF Descargar | [ Datasheet NL128102BC29-01.PDF ] |
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