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Número de pieza | SSM6P49NU | |
Descripción | Field Effect Transistor | |
Fabricantes | Toshiba Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de SSM6P49NU (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
No Preview Available ! SSM6P49NU
TOSHIBA Field Effect Transistor Silicon P Channel MOS Type
SSM6P49NU
Power Management Switch Applications
• 1.8V drive
• Low ON-resistance: RDS(on) = 157 mΩ (max) (@VGS = -1.8 V)
RDS(on) = 76 mΩ (max) (@VGS = -2.5 V)
RDS(on) = 56 mΩ (max) (@VGS = -4.5 V)
RDS(on) = 45 mΩ (max) (@VGS = -10V)
2.0±0.1
Unit: mm
B
A
Absolute Maximum Ratings (Ta = 25°C) (Q1, Q2
Common)
0~0.05
0.13
Characteristics
Drain-Source voltage
Symbol
VDSS
Rating
−20
Unit
V
*BOTTOM VIEW
1
0.65 0.65
0.95
2
3
Gate-Source voltage
VGSS ±12 V
Drain current
DC
Pulse
Power dissipation (Note 2)
ID
IDP (Note 1)
PD
t < 10s
−4.0
−16.0
1
2
A
W
6
0.3±0.075
0.05 M A B
5
0.65±0.075
4
0.65±0.075
0.05 M A B
1. Source1 4. Source2
Channel temperature
Storage temperature
Tch 150 °C
Tstg
−55 to 125
°C
UDFN6
2. Gate1 5. Gate2
3. Drain2 6. Drain1
Note: Using continuously under heavy loads (e.g. the application of
JEDEC
―
high temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
JEITA
TOSHIBA
―
2-1Y1A
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Weight: 8.5 mg (typ.)
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: The pulse width limited by max channel temperature.
Note 2: Total rating
Mounted on an FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
Marking(Top View)
65 4
Equivalent Circuit(Top View)
65 4
Pin Condition(Top View)
D1 G2 S2
PP5
Q1
Q2
D1 D2
1 23
Polarity marking
1 23
S1 G1 D2
Polarity marking (on the top)
*Electrodes: on the bottom
Start of commercial production
2010-11
1 2014-03-01
1 page 1000
Rth – tw
b
100
a
10
1
0.001
Single pulse
a. Mounted on F4 board
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
b. Mounted on F4 board
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 2.13 mm2)
0.01
0.1
1
10
100 1000
Pulse width tw (s)
SSM6P49NU
PD – Ta
1400 a: Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm , Cu Pad : 645 mm2)
b: Mounted on FR4 board
1200 (25.4mm × 25.4mm × 1.6mm , Cu Pad : 2.13mm2 )
1000
800
a
600
400
b
200
0
-40 -20 0 20 40 60 80 100 120 140 160
Ambient temperature Ta (°C)
5 2014-03-01
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet SSM6P49NU.PDF ] |
Número de pieza | Descripción | Fabricantes |
SSM6P49NU | Field Effect Transistor | Toshiba Semiconductor |
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