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PDF SSM3J56MFV Data sheet ( Hoja de datos )

Número de pieza SSM3J56MFV
Descripción Field Effect Transistor Silicon
Fabricantes Toshiba Semiconductor 
Logotipo Toshiba Semiconductor Logotipo



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SSM3J56MFV
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOS)
SSM3J56MFV
Load Switching Applications
1.2 V drive
Low ON-resistance:RDS(ON) = 390 m(max) (@VGS = -4.5 V)
RDS(ON) = 480 m(max) (@VGS = -2.5 V)
RDS(ON) = 660 m(max) (@VGS = -1.8 V)
RDS(ON) = 900 m(max) (@VGS = -1.5 V)
RDS(ON) = 4000 m(max) (@VGS = -1.2 V)
Unit: mm
Absolute Maximum Ratings (Ta = 25°C)
Characteristic
Symbol
Rating
Unit
Drain-Source voltage
Gate-Source voltage
Drain current
DC
Pulse
Power dissipation
Channel temperature
Storage temperature range
VDSS
VGSS
ID (Note 1)
IDP (Note 1)
PD (Note 2)
PD (Note 3)
t < 5s
Tch
Tstg
-20
±8
-800
-1600
150
500
800
150
55 to 150
V
V
mA
mW
°C
°C
VESM
1.Gate
2.Source
3.Drain
Note: Using continuously under heavy loads (e.g. the application of high
JEDEC
temperature/current/voltage and the significant change in
JEITA
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
TOSHIBA
2-1L1B
operating temperature/current/voltage, etc.) are within the
Weight: 1.5mg (typ.)
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: The channel temperature should not exceed 150°C during use.
Note 2: Mounted on a FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.585 mm2)
Note 3: Mounted on a FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
Marking
3
Equivalent Circuit (top view)
3
PW
12
Handling Precaution
12
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
Thermal resistance Rth (ch-a) and Power dissipation PD vary depending on board material, board area, board thickness
and pad area. When using this device, please take heat dissipation into consideration.
1 2011-05-09

1 page




SSM3J56MFV pdf
1000
100
Rth – tw
b
a
10
1
0.001
Single pulse
a: Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6
mm,
Cu
Pad:
645
mm2)
b: Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6
mm,
Cu
Pad:
0.585
mm2)
0.01
0.1
1
10 100 1000
Pulse Width tw (s)
SSM3J56MFV
600
a
500
400
PD – Ta
a: Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm,
Cu Pad : 645 mm2)
b: Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm,
Cu Pad : 0.585 mm2)
300
200
b
100
0
0 50 100 150
Ambient temperature Ta (°C)
5 2011-05-09

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