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Número de pieza | TK8A10K3 | |
Descripción | Field Effect Transistor | |
Fabricantes | Toshiba Semiconductor | |
Logotipo | ||
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TOSHIBA Field Effect Transistor Silicon N-Channel MOS Type (U-MOS )
TK8A10K3
Swiching Regulator Applications
• Low drain-source ON resistance: RDS (ON) = 90 mΩ (typ.)
• Low leakage current: IDSS = 10 µA (max) (VDS = 100 V)
• Enhancement-model: Vth = 2.0 to 4.0 V (VDS = 10 V, ID = 1.0 mA)
Unit: mm
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Drain-source voltage
VDSS 100 V
Drain-gate voltage (RGS = 20 kΩ)
VDGR
100
V
Gate-source voltage
VGSS ±20 V
Drain current
DC (Note 1)
Pulse (Note 1)
ID
IDP
8
A
16
Drain power dissipation (Tc = 25°C)
PD
18 W
Single pulse avalanche energy
(Note 2)
Avalanche current
Channel temperature
EAS
IAR
Tch
4 mJ
8A
150 °C
1: Gate
2: Drain
3: Source
Storage temperature range
Tstg
−55 to 150
°C
JEDEC
⎯
Note :
Using continuously under heavy loads (e.g. the application of
high temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
JEITA
TOSHIBA
SC-67
2-10U1B
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
Weight: 1.7 g (typ.)
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: Please use devices on condition that the channel temperature is below 150°C.
Note 2: VDD = 25 V, Tch = 25°C, L = 100 µH, RG = 25 Ω, IAR = 8 A
Thermal Characteristics
2
Characteristics
Thermal resistance, channel to case
Thermal resistance, channel to
ambient
Symbol
Rth (ch−c)
Rth (ch−a)
Max
6.94
62.5
Unit
°C / W
°C / W
This transistor is an electrostatic sensitive device. Please handle with caution.
1
3
1 2009-08-11
1 page TK8A10K3
rth /Rth (ch-c) – tw
10
1
Duty = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
10 µ
SINGLE PULSE
PDM
t
T
0.01
Duty = t/T
Rth (ch-c) = 6.94°C/W
100 µ
1m
10 m
100 m
1
10
Pulse width tw (s)
Safe operating area
100
ID max (Pulse) *
10
t = 100 µs *
1 ms *
1
* Single - pulse Ta = 25
Curves must be derated
linearly with increase in
temperature.
0.1
1
10
VDSS max
100
Drain-source voltage VDS (V)
1000
EAS – Ta
10 L = 100 uH
VDD = 25 V
IAR = 8 A
8
6
4
2
0
25 50 75 100 125 150
Channel temperature (initial) Tch (°C)
15 V
−15 V
Test circuit
RG = 25 Ω
VDD = 25 V, L = 100 µH
BVDSS
IAR
VDD
VDS
Wave form
ΕAS
=
1
2
⋅L ⋅I2
⋅
⎜⎜⎝⎛
BVDSS
BVDSS − VDD
⎟⎟⎠⎞
5 2009-08-11
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet TK8A10K3.PDF ] |
Número de pieza | Descripción | Fabricantes |
TK8A10K3 | Field Effect Transistor | Toshiba Semiconductor |
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