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PDF MEC1310 Data sheet ( Hoja de datos )
| Número de pieza | MEC1310 | |
| Descripción | Keyboard and Embedded Controller | |
| Fabricantes | Microchip | |
| Logotipo |  |
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MEC1310
Keyboard and Embedded Controller for Notebook PC
Product Features
• 3.3V Operation with 5V Tolerant Buffers on PS/2
pins
• ACPI 1.0/2.0 PC99/PC2001 Compliant
• LPC Interface with Clock Run Support
- Supports LPC Bus frequencies of 19.2MHz to
33MHz
- Serial IRQ Interface Compatible with Serial-
ized IRQ Support for PCI Systems
- 15 Direct IRQs
- ACPI SCI Interface
- nSMI output and supporting PM registers
- Shadowed write only registers
• Internal 64K SRAM in MEC1310
- Loaded at VCC1 power from the HOST/8051
SPI Memory Interface
- Provides 64KB of 8051 program space
- 32k-Byte region shared with 8051data space
• HOST/8051 SPI Memory Interface
- 3-pin Full Duplex serial communication inter-
face.
- One Chip Select Pins
- Fully 8051 Controlled
- Hardware Support for two SPI Flash Configu-
rations:
– Switched SPI Flash Configuration
– Parallel Shared SPI Flash Configuration
– Debug Programming Interface
• Two Power Planes
- Low Standby Current in Sleep Mode
• Three ACPI Embedded Controller Interface
• Configuration Register Set Compatible with ISA
Plug-and-Play Standard (Version 1.0a)
• High-Performance Embedded 8051 Keyboard
and System Controller
- Provides System Power Management
- System Watch Dog Timer (WDT)
- 8042 Style Host Interface
- Supports Interrupt and Polling Access
- 1024 Boot /ROM
- 256 Bytes Data RAM
- On-Chip Memory-Mapped Control Registers
- Access to VCC0 Backed Registers
- Up to 18x8 Keyboard Scan Matrix
- Two 16-Bit Timer/Counters
- Integrated Full-Duplex Serial Port Interface
- Seventy-Three 8051 Interrupt Sources
- Thirty-Two 8-Bit, Host/8051 Mailbox Regis-
ters
- Sixty-Four Maskable Hardware Wake-Up
Events
- Fast GATEA20
- Fast CPU_RESET
- Multiple Clock Sources and Operating Fre-
quencies
- IDLE and SLEEP Modes
- Trace FIFO Debug Port
• Accurate Fail-Safe Ring Oscillator
- Single Clock source for most 8051 and SIO
functions
- Provides 2% frequency accuracy
- Lock Bit provides status
- 32.768KHz-input clock
– Single ended input
– Compatible with south bridge SUSCLK/
RSMRST# gating rules
– replacement 32K distribution available when
RSMRST# is asserted
– Very low power state with only external 32K clock
distributed
• Integrated Standby Power Reset Generator
- VCC1_RST# open drain output
- Accepts External driven Reset
• VCC0 Backed Resources
- 64 Byte VCC0 Backed Registers
- VCC0 Backed Status Register
• Three 8584-Style I2C/SMBus Controllers
- 8051 Controlled Logic Allows I2C/SMBus
Master or Slave Operation
- I2C/SMBus Controllers are Fully Operational
on Standby Power
- Two Controllers with 2 Sets of Dedicated Pins
per I2C/SMBus Controller
- One Controller with one Set of Dedicated
Pins per I2C/SMBus Controller
• Four independent Hardware Driven PS/2 Ports
- GPIO signal function associated with each
pin
• PECI Interface 2.0
2014 Microchip Technology Inc.
DS00001768A-page 1
1 page  
MEC1310
PACKAGE OUTLINE
FIGURE 2:
MEC1310 128-PIN VTQFP PACKAGE OUTLINE 14X14X1.0
2014 Microchip Technology Inc.
DS00001768A-page 5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MEC1310.PDF ] | |
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