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PDF ARM7TDMI Data sheet ( Hoja de datos )
| Número de pieza | ARM7TDMI | |
| Descripción | Technical Reference Manual | |
| Fabricantes | ARM | |
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ARM7TDMI
Revision: r4p1
Technical Reference Manual
Copyright © 2001, 2004 ARM Limited. All rights reserved.
ARM DDI 0210C
1 page  
Contents
Chapter 7
Appendix A
Appendix B
Appendix C
6.14 Coprocessor data transfer from memory to coprocessor .......................... 6-21
6.15 Coprocessor data transfer from coprocessor to memory .......................... 6-23
6.16 Coprocessor register transfer, load from coprocessor .............................. 6-25
6.17 Coprocessor register transfer, store to coprocessor ................................. 6-26
6.18 Undefined instructions and coprocessor absent ....................................... 6-27
6.19 Unexecuted instructions ............................................................................ 6-28
6.20 Instruction speed summary ....................................................................... 6-29
AC and DC Parameters
7.1 Timing diagrams ......................................................................................... 7-2
7.2 Notes on AC parameters .......................................................................... 7-20
7.3 DC parameters .......................................................................................... 7-26
Signal and Transistor Descriptions
A.1 Transistor dimensions ................................................................................. A-2
A.2 Signal types ................................................................................................ A-3
A.3 Signal descriptions ...................................................................................... A-4
Debug in Depth
B.1 Scan chains and the JTAG interface .......................................................... B-3
B.2 Resetting the TAP controller ....................................................................... B-6
B.3 Pullup resistors ........................................................................................... B-7
B.4 Instruction register ...................................................................................... B-8
B.5 Public instructions ....................................................................................... B-9
B.6 Test data registers .................................................................................... B-14
B.7 The ARM7TDMI core clocks ..................................................................... B-22
B.8 Determining the core and system state in debug state ............................. B-24
B.9 Behavior of the program counter in debug state ....................................... B-30
B.10 Priorities and exceptions ........................................................................... B-33
B.11 Scan chain cell data .................................................................................. B-35
B.12 The watchpoint registers ........................................................................... B-42
B.13 Programming breakpoints ......................................................................... B-47
B.14 Programming watchpoints ......................................................................... B-50
B.15 The debug control register ........................................................................ B-51
B.16 The debug status register ......................................................................... B-54
B.17 The abort status register ........................................................................... B-56
B.18 Coupling breakpoints and watchpoints ..................................................... B-57
B.19 EmbeddedICE-RT timing .......................................................................... B-59
B.20 Programming restriction ............................................................................ B-60
Differences Between Rev 3a and Rev 4
C.1 Summary of differences between Rev 3a and Rev 4 ................................. C-2
C.2 Detailed descriptions of differences between Rev 3a and Rev 4 ............... C-3
Glossary
ARM DDI 0210C
Copyright © 2001, 2004 ARM Limited. All rights reserved.
v
5 Page 
List of Figures
ARM7TDMI Technical Reference Manual
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 1-6
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Key to timing diagram conventions .......................................................................... xviii
Instruction pipeline .................................................................................................... 1-2
ARM7TDMI processor block diagram ....................................................................... 1-8
ARM7TDMI main processor logic ............................................................................. 1-9
ARM7TDMI processor functional diagram .............................................................. 1-10
ARM instruction set formats .................................................................................... 1-12
Thumb instruction set formats ................................................................................. 1-21
LIttle-endian addresses of bytes and halfwords within words ................................... 2-4
Big-endian addresses of bytes and halfwords within words ...................................... 2-5
Register organization in ARM state ........................................................................... 2-9
Register organization in Thumb state ..................................................................... 2-10
Mapping of Thumb-state registers onto ARM-state registers .................................. 2-11
Program status register format ................................................................................ 2-13
Simple memory cycle ................................................................................................ 3-4
Nonsequential memory cycle .................................................................................... 3-6
Sequential access cycles .......................................................................................... 3-7
Internal cycles ........................................................................................................... 3-8
Merged IS cycle ........................................................................................................ 3-9
Coprocessor register transfer cycles ....................................................................... 3-10
Memory cycle timing ............................................................................................... 3-10
Pipelined addresses ................................................................................................ 3-14
Depipelined addresses ............................................................................................ 3-15
SRAM compatible address timing ........................................................................... 3-16
ARM DDI 0210C
Copyright © 2001, 2004 ARM Limited. All rights reserved.
xi
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