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PDF CY7C0832V Data sheet ( Hoja de datos )
| Número de pieza | CY7C0832V | |
| Descripción | Synchronous Dual-Port RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
PRELIMINARY
CY7C0837V
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
FLEx18TM 3.3V 32K/64K/128K/256K/512K x 18
Synchronous Dual-Port RAM
Features
Functional Description
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• Synchronous pipelined operation
• Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit
devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
• 120TQFP (14 mm x 14 mm x 1.4 mm)
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
The FLEx18 family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit
and 9-Mbit pipelined, synchronous, true dual-port static RAMs
that are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location
by more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0833V device in this family has limited features.
Please see Address Counter and Mask Register
Operations[15] on page 6 for details.
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time - clock to Data (ns)
Typical operating current (mA)
Package
512-Kbit
(32K x 18)
CY7C0837V
167
4.0
225
144 FBGA
1-Mbit
(64K x 18)
CY7C0830V
167
4.0
225
120 TQFP
144 FBGA
2-Mbit
(128K x 18)
CY7C0831V
167
4.0
225
120 TQFP
144 FBGA
4-Mbit
(256K x 18)
CY7C0832V
167
4.0
225
120 TQFP
144 FBGA
9-Mbit
(512K x 18)
CY7C0833V
133
4.7
270
144 FBGA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06059 Rev. *K
July 06, 2004
1 page  
PRELIMINARY
CY7C0837V
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
Pin Definitions
Left Port
A0L–A18L[1]
ADSL[7]
CE0L[7]
CE1L[6]
CLKL
CNTENL[7]
Right Port
A0R–A18R[1]
ADSR[7]
CE0R[7]
CE1R[6]
CLKR
CNTENR[7]]
Description
Address Inputs.
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW
for the part using the externally supplied address on the address pins and for loading this
address into the burst address counter.
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
Clock Signal. Maximum clock input rate is fMAX.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of
its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST
are asserted LOW.
CNTRSTL[6]
CNTRSTR[6]
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of
the burst address counter of its respective port. CNTRST is not disabled by asserting ADS
or CNTEN.
CNT/MSKL[6]
DQ0L–DQ17L[1]
OEL
CNT/MSKR[6]
DQ0R–DQ17R[1]
OER
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access
to the mask register. When tied HIGH, the mask register is not accessible and the address
counter operations are enabled based on the status of the counter control signals.
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
CNTINTL[8]
CNTINTR[8]
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the
counter is incremented to all “1s.”
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
B0L–B3L
B0R–B1R
Byte Select Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
Asserting MRST LOW performs all of the reset functions as described in the text. A MRST
operation is required at power-up.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS Ground Inputs.
VDD Power Inputs.
Document #: 38-06059 Rev. *K
Page 5 of 28
5 Page 
PRELIMINARY
CY7C0837V
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
TDO
D2
TDI
TDO
TDO
D1
TDI
TDI
Figure 3. Scan Chain for 9Mb Device
Table 4. Identification Register Definitions
Instruction Field
Revision Number (31:28)
Value
0h
Description
Reserved for version number.
Cypress Device ID (27:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
C090h
C091h
C093h
C094h
034h
1
Defines Cypress part number for CY7C0832V
Defines Cypress part number for CY7C0831V
Defines Cypress part number for CY7C0830V
Defines Cypress part number for CY7C0837V.
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Table 5. Scan Registers Sizes
Register Name
Instruction
Bypass
Identification
Boundary Scan
Bit Size
4
1
32
n[21]
Table 6. Instruction Identification Codes
Instruction
Code
EXTEST
0000
BYPASS
1111
IDCODE
1011
HIGHZ
0111
CLAMP
0100
SAMPLE/PRELOAD 1000
NBSRST
1100
RESERVED
All other codes
Notes:
21. See details in the device BSDL file.
Description
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
Other combinations are reserved. Do not use other than the above.
Document #: 38-06059 Rev. *K
Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet CY7C0832V.PDF ] | |
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