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PDF PSMN2R8-80BS Data sheet ( Hoja de datos )

Número de pieza PSMN2R8-80BS
Descripción N-channel standard level FET
Fabricantes NXP Semiconductors 
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PSMN2R8-80BS
N-channel 80 V, 3 mstandard level FET in D2PAK
Rev. 2 — 29 February 2012
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel MOSFET in D2PAK package qualified to 175C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for standard level gate drive
1.3 Applications
DC-to-DC converters
Load switch
Motor control
Server power supplies
1.4 Quick reference data
Table 1. Quick reference data
Symbol
Parameter
VDS drain-source voltage
ID drain current
Ptot total power dissipation
Tj junction temperature
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
QGD gate-drain charge
QG(tot)
total gate charge
Avalanche ruggedness
EDS(AL)S
non-repetitive
drain-source
avalanche energy
Conditions
Tj 25 °C; Tj 175 °C
Tmb = 25 °C; VGS = 10 V; see Figure 1
Tmb = 25 °C; see Figure 2
VGS = 10 V; ID = 25 A; Tj = 100 °C;
see Figure 12; see Figure 13
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 13
VGS = 10 V; ID = 75 A; VDS = 40 V;
see Figure 14; see Figure 15
VGS = 10 V; Tj(init) = 25 °C; ID = 120 A;
Vsup 80 V; RGS = 50 ; unclamped
[1] Continuous current is limited by package.
Min Typ Max Unit
- - 80 V
[1] - - 120 A
- - 306 W
-55 -
175 °C
-
4.21 5
m
-
2.55 3
m
- 27 - nC
- 139 - nC
- - 676 mJ

1 page




PSMN2R8-80BS pdf
NXP Semiconductors
PSMN2R8-80BS
N-channel 80 V, 3 mstandard level FET in D2PAK
6. Characteristics
Table 6. Characteristics
Symbol
Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source
breakdown voltage
gate-source threshold
voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 10
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 10
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10; see Figure 11
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
VDS = 80 V; VGS = 0 V; Tj = 25 °C
VDS = 80 V; VGS = 0 V; Tj = 175 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 25 A; Tj = 175 °C;
see Figure 12; see Figure 13
VGS = 10 V; ID = 25 A; Tj = 100 °C;
see Figure 12; see Figure 13
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 13
RG internal gate resistance f = 1 MHz
(AC)
Dynamic characteristics
QG(tot)
QGS
QGS(th)
total gate charge
gate-source charge
pre-threshold
gate-source charge
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 75 A; VDS = 40 V; VGS = 10 V;
see Figure 14; see Figure 15
QGS(th-pl)
post-threshold
gate-source charge
QGD
VGS(pl)
gate-drain charge
gate-source plateau
voltage
ID = 75 A; VDS = 40 V;see Figure 14;
see Figure 15
Ciss
Coss
Crss
input capacitance
output capacitance
reverse transfer
capacitance
VDS = 40 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
td(on)
tr
td(off)
tf
turn-on delay time
rise time
turn-off delay time
fall time
VDS = 40 V; RL = 0.53 ; VGS = 5 V;
RG(ext) = 10 ; ID = 75 A
Min Typ Max Unit
73 - - V
80 - - V
1- - V
- - 4.6 V
234V
- 0.02 10 µA
- - 500 µA
- 10 100 nA
- 10 100 nA
- 6.12 7.2 m
-
4.21 5
m
-
2.55 3
m
- 0.9 -
- 135 - nC
- 139 - nC
- 51 - nC
- 30 - nC
- 21 - nC
- 27 - nC
- 5.8 - V
- 9961 - pF
- 847 - pF
- 401 - pF
- 41 - ns
- 43 - ns
- 109 - ns
- 44 - ns
PSMN2R8-80BS
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 29 February 2012
© NXP B.V. 2012. All rights reserved.
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PSMN2R8-80BS arduino
NXP Semiconductors
PSMN2R8-80BS
N-channel 80 V, 3 mstandard level FET in D2PAK
8. Revision history
Table 7. Revision history
Document ID
Release date
Data sheet status
PSMN2R8-80BS v.2
Modifications:
20120229
Product data sheet
Status changed from objective to product.
Various changes to content.
PSMN2R8-80BS v.1 20110928
Objective data sheet
Change notice
-
-
Supersedes
PSMN2R8-80BS v.1
-
PSMN2R8-80BS
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 29 February 2012
© NXP B.V. 2012. All rights reserved.
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