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PDF PSMN3R0-30YL Data sheet ( Hoja de datos )
| Número de pieza | PSMN3R0-30YL | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | NXP Semiconductors | |
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PSMN3R0-30YL
N-channel 30 V 3 mΩ logic level MOSFET in LFPAK
Rev. 04 — 10 March 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converters
Motor control
Server power supplies
1.4 Quick reference data
Table 1. Quick reference data
Symbol
VDS
ID
Parameter
drain-source voltage
drain current
Conditions
Tj ≥ 25 °C; Tj ≤ 175 °C
Tmb = 25 °C; VGS = 10 V;
see Figure 1
Ptot total power dissipation
Tj junction temperature
Static characteristics
Tmb = 25 °C; see Figure 2
RDSon
drain-source on-state
resistance
Dynamic characteristics
VGS = 10 V; ID = 15 A;
Tj = 25 °C
QGD
gate-drain charge
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14;
see Figure 15
QG(tot)
total gate charge
Avalanche ruggedness
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C;
drain-source avalanche ID = 100 A; Vsup ≤ 30 V;
energy
RGS = 50 Ω; unclamped
Min Typ Max Unit
- - 30 V
[1] - - 100 A
--
-55 -
81 W
175 °C
- 2.19 3 mΩ
- 5.1 - nC
- 21 - nC
- - 75 mJ
[1] Continuous current is limited by package.
1 page  
NXP Semiconductors
PSMN3R0-30YL
N-channel 30 V 3 mΩ logic level MOSFET in LFPAK
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
thermal resistance from junction to mounting see Figure 4
base
Min Typ Max Unit
- 0.9 1.5 K/W
10
Zth(j-mb)
(K/W)
003aac573
1
δ = 0.5
0.2
10-1 0.1
0.05
P δ = tp
T
0.02
single shot
10-2
tp
T
t
10-6
10-5
10-4
10-3
10-2
10-1 tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN3R0-30YL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 10 March 2011
© NXP B.V. 2011. All rights reserved.
5 of 15
5 Page 
NXP Semiconductors
PSMN3R0-30YL
N-channel 30 V 3 mΩ logic level MOSFET in LFPAK
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
L1
HD
E
A
A2
C
b2 c2
mounting
base
D1
L2
1 2 34
e b wM A
1/2 e
X
c
E1
b3
b4
A
A1 C
detail X
(A3)
θ
L
yC
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A
A1 A2 A3
b
b2 b3 b4
c
c2
D (1)
D1(1)
max
E(1)
E1(1)
e
H
L L1
mm 1.20 0.15 1.10 0.25 0.50 4.41 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 1.27 6.2 0.85 1.3
1.01 0.00 0.95
0.35 3.62 2.0 0.7 0.19 0.24 3.80
4.8 3.1
5.8 0.40 0.8
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
L2 w y
1.3 0.25 0.1
0.8
θ
8°
0°
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT669
MO-235
EUROPEAN
PROJECTION
ISSUE DATE
04-10-13
06-03-16
Fig 18. Package outline SOT669 (LFPAK)
PSMN3R0-30YL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 10 March 2011
© NXP B.V. 2011. All rights reserved.
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