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| Número de pieza | PSMN3R9-25MLC | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | NXP Semiconductors | |
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PSMN3R9-25MLC
N-channel 25 V 4.15 mΩ logic level MOSFET in LFPAK33
using NextPower Technology
Rev. 4 — 15 June 2012
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK33 package. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
Low parasitic inductance and
resistance
Optimised for 4.5V Gate drive utilising
NextPower Superjunction technology
Ultra low QG, QGD, & QOSS for high
system efficiencies at low and high
loads
1.3 Applications
DC-to-DC converters
Load switching
Synchronous buck regulator
1.4 Quick reference data
Table 1. Quick reference data
Symbol
Parameter
VDS drain-source voltage
ID drain current
Ptot total power dissipation
Tj junction temperature
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
QGD gate-drain charge
QG(tot)
total gate charge
Conditions
Tj = 25°C
Tmb = 25 °C; VGS = 10 V; see Figure 1
Tmb = 25 °C; see Figure 2
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
see Figure 10
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 10
VGS = 4.5 V; ID = 25 A; VDS = 12.5 V;
see Figure 12; see Figure 13
VGS = 4.5 V; ID = 25 A; VDS = 12.5 V;
see Figure 12; see Figure 13
[1] Continuous current is limited by package.
Min Typ Max Unit
- - 25 V
[1] - - 70 A
- - 69 W
-55 -
175 °C
- 4.85 5.55 mΩ
- 3.65 4.15 mΩ
- 2.3 - nC
- 9.7 - nC
1 page  
NXP Semiconductors
PSMN3R9-25MLC
N-channel 25 V 4.15 mΩ logic level MOSFET in LFPAK33 using NextPower Technology
6. Characteristics
Table 6. Characteristics
Symbol
Parameter
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
VGS(th)
∆VGS(th)/∆T
IDSS
gate-source threshold
voltage
gate-source threshold
voltage variation with
temperature
drain leakage current
IGSS gate leakage current
RDSon
drain-source on-state
resistance
RG gate resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
QGS(th)
QGS(th-pl)
QGD
VGS(pl)
Ciss
Coss
Crss
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
Conditions
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 1 mA; VDS = VGS; Tj = 25 °C
VDS = 25 V; VGS = 0 V; Tj = 25 °C
VDS = 25 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
see Figure 10
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
see Figure 10; see Figure 11
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 10
VGS = 10 V; ID = 25 A; Tj = 150 °C;
see Figure 10; see Figure 11
f = 1 MHz
ID = 25 A; VDS = 12.5 V; VGS = 10 V;
see Figure 12; see Figure 13
ID = 25 A; VDS = 12.5 V; VGS = 4.5 V;
see Figure 12; see Figure 13
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 25 A; VDS = 12.5 V; VGS = 4.5 V;
see Figure 12; see Figure 13
ID = 25 A; VDS = 12.5 V; see Figure 12;
see Figure 13
VDS = 12.5 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 14
Min Typ Max Unit
25 - - V
22.5 - - V
1.45 1.81 2.15 V
- -4.1 - mV/K
- - 1 µA
- - 100 µA
- - 100 nA
- - 100 nA
- 4.85 5.55 mΩ
- - 8.9 mΩ
- 3.65 4.15 mΩ
- - 6.65 mΩ
0.9 1.8 3.6 Ω
- 21.5 - nC
- 9.7 - nC
- 20.9 - nC
- 3.9 - nC
- 2.4 - nC
- 1.5 - nC
- 2.3 - nC
- 2.9 - V
- 1524 - pF
- 376 - pF
- 128 - pF
PSMN3R9-25MLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 15 June 2012
© NXP B.V. 2012. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
PSMN3R9-25MLC
N-channel 25 V 4.15 mΩ logic level MOSFET in LFPAK33 using NextPower Technology
8. Revision history
Table 7. Revision history
Document ID
Release date
Data sheet status
PSMN3R9-25MLC v.4 20120615
Product data sheet
Modifications:
• Various changes to content.
PSMN3R9-25MLC v.3 20120607
Product data sheet
Change notice
-
-
Supersedes
PSMN3R9-25MLC v.3
PSMN3R9-25MLC v.2
PSMN3R9-25MLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 15 June 2012
© NXP B.V. 2012. All rights reserved.
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