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PDF MT9N001 Data sheet ( Hoja de datos )
| Número de pieza | MT9N001 | |
| Descripción | 1/2.3-Inch 9Mp CMOS Digital Image Sensor | |
| Fabricantes | Aptina Imaging Corporation | |
| Logotipo |  |
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Aptina Confidential and Proprietary
MT9N001: 1/2.3-Inch 9Mp CMOS Digital Image Sensor
Features
1/2.3-Inch 9Mp CMOS Digital Image Sensor
MT9N001 Data Sheet
For the latest data sheet, refer to Aptina’s Web site: www.aptina.com
Features
• DigitalClarity® CMOS imaging technology
• Simple two-wire serial interface
• Auto black level calibration
• Support for external mechanical shutter
• Support for external LED or xenon flash
• High frame rate preview mode with arbitrary down-
size scaling from maximum resolution
• Programmable controls: gain, horizontal and vertical
blanking, auto black level offset correction, frame
size/rate, exposure, left–right and top–bottom image
reversal, window size, and panning
• Data interfaces: parallel- or CCP2-compliant sub-
low-voltage differential signalling (sub-LVDS) or
one/two lane serial mobile industry processor
interface (MIPI)
• On-die phase-locked loop (PLL) oscillator
• Bayer pattern down-size scaler
• Integrated position-based color and lens shading
correction
• One-time programmable (OTP) memory for storing
module information
Applications
• Cellular phones
• Digital still cameras
• PC cameras
• PDAs
General Description
The Aptina MT9N001 is a 1/2.3-inch CMOS active-
pixel digital image sensor with a pixel array of
3488H x 2616V including border pixels. It incorporates
sophisticated on-chip camera functions such as win-
dowing, mirroring, column and row skip modes, and
snapshot mode. It is programmable through a simple
two-wire serial interface and has very low power con-
sumption.
Table 1:
Key Performance Parameters
Parameter
Optical format
Active imager size
Active pixels
Pixel size
Chief ray angle
Color filter array
Shutter type
Input clock frequency
Parallel
Maximum CCP2
data rate MIPI (two-lane)
Full resolution
Frame rate
VGA
ADC resolution
Responsivity
Dynamic range
SNRMAX
I/O Digital
Supply
voltage Digital
Analog
Power
Full resolution
Consump- Preview
tion Standby
Package
Operating temperature
Value
1/2.3-inch (4:3)
6.104mm(H) x 4.578mm(V)
7.63mm diagonal
3488H x 2616V
1.75 x 1.75μm
0°
RGB Bayer pattern
Electronic rolling shutter (ERS)
with global reset release (GRR)
6–48 MHz
96 Mp/s at 96 MHz PIXCLK
640 Mbps
1.536 Gbps
Programmable up to 13.2 fps
serial, 9.7 fps parallel
30 fps VGA binning with
8Mp field-of-view
12-bit, on-die
0.44 V/lux-sec (550nm)
65dB
35dB
1.7–1.9V (1.8V nominal)
or 2.4–3.1V (2.8V nominal)
1.7–1.9V (1.8V nominal)
2.6–3.1V (2.8V nominal)
500mW
210mW low power VGA
500μW (typical, EXTCLK disabled)
48-pin iLCC (10mm x 10mm)
Bare die
–30°C to +70°C (at junction)
Ordering Information
Table 2:
Available Part Numbers
Part Number
MT9N001D00STCC2BBC1
MT9N001I12STC
Description
Bare die
48-pin iLCC
PDF: 2890213592/Source: 2055621246
MT9N001_DS - Rev. D 1/10 EN
1 Aptina reserves the right to change products or specifications without notice.
©2007 Aptina Imaging Corporation All rights reserved.
Products and specifications discussed herein are subject to change by Aptina without notice.
1 page  
Aptina Confidential and Proprietary
MT9N001: 1/2.3-Inch 9Mp CMOS Digital Image Sensor
List of Figures
List of Figures
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Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Configuration: Serial CCP2 Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Typical Configuration: Serial Two-Lane MIPI Pixel Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical Configuration: CCP2 Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Typical Configuration: Parallel MIPI Pixel Data Interface (MIPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
48-Pin iLCC Package Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Pixel Data Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Row Timing and FV/LV Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Single READ from Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Effect of Limiter on the Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Timing of Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MT9N001 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Sequence for Programming the MT9N001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Effect of horizontal_mirror on Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Effect of vertical_flip on Readout Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Effect of x_odd_inc = 3 on Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Effect of x_odd_inc = 7 on Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Pixel Readout (No Subsampling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Pixel Readout (x_odd_inc = 3, y_odd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Pixel Readout (x_odd_inc = 7, y_odd_inc = 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Pixel Readout (x_odd_inc = 7, y_odd_inc = 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Pixel Readout (x_odd_inc = 7, y_odd_inc = 31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Pixel Readout (x_odd_inc = 7, y_odd_inc = 63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Pixel Readout (x_odd_inc = 3, y_odd_inc = 1, x_bin = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Pixel Readout (x_odd_inc = 3, y_odd_inc = 3, xy_bin = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Pixel Readout (x_odd_inc = 7, y_odd_inc = 7, xy_bin = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Xenon Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
LED Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
LED Flash Enabled Following Forced Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Overview of Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Entering and Leaving a Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Controlling the Reset and Integration Phases of the Global Reset Sequence . . . . . . . . . . . . . . . . . . . .61
Control of the Electromechanical Shutter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Controlling the SHUTTER Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Using FLASH with Global Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Global Reset Bulb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Entering Soft Standby During a Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Test Cursor Behavior with image_orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Hard Standby and Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Soft Standby and Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Two-WIre Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
48-Pin iLCC Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PDF: 2890213592/Source: 2055621246
MT9N001_DS - Rev. D 1/10 EN
5 Aptina reserves the right to change products or specifications without notice.
©2007 Aptina Imaging Corporation. All rights reserved.
5 Page 
Figure 4:
Aptina Confidential and Proprietary
MT9N001: 1/2.3-Inch 9Mp CMOS Digital Image Sensor
Operating Modes
Typical Configuration: Serial Two-Lane MIPI Pixel Data Interface
Digital Digital Digital
I/O Core
PHY
power1 power1 power1
PLL Analog Analog
power1 power1 power1
VDD_IO VDD VDD_TX0 VDD_PLL VAA VAA_PIX
Master clock
(6–48 MHz)
From
controller
EXTCLK
SDATA
SCLK
RESET_BAR
TEST
GND_PLL DGND PIXGND
DATA0_P
DATA0_N
DATA1_P
DATA1_N
CLK_P
CLK_N
AGND
To
controller
VDD_IO
VDD VDD_TX0 VDD_PLL
VAA VAA_PIX
Digital
ground
Analog
ground
Notes:
1. All power supplies should be adequately decoupled.
2. Aptina recommends a resistor value of 1.5kΩ, but it may be greater for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. VPP, which can be used during the module manufacturing process, is not shown in Figure 4. This pad is
left unconnected during normal operation.
5. The parallel interface output pads can be left unconnected if the serial output interface is used.
6. Aptina recommends that 0.1μF and 10μF decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design consid-
erations.
7. Aptina recommends that VDD_TX0 be tied to VDD.
8. Aptina recommends that analog power planes are placed in a manner such that coupling with the digi-
tal power planes is minimized.
PDF: 2890213592/Source: 2055621246
MT9N001_DS - Rev. D 1/10 EN
11
Aptina reserves the right to change products or specifications without notice.
©2007 Aptina Imaging Corporation. All rights reserved.
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet MT9N001.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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