PDF DSP32C Data sheet ( Hoja de datos )

Número de pieza	DSP32C
Descripción	Digital Signal Processor
Fabricantes	Lucent Technologies
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No Preview Available ! Data Sheet Addendum November 1996 DSP32C Digital Signal Processor Products Affected This advisory is effective for issue 5 of the DSP32C. Issue 5 devices are identiﬁed by a device code of the form DSP32C-X35 (where X is replaced by R or F). The design consideration involves external writes to and reads from the parallel data register (PDR) with a system clock greater than 66 MHz. Problem Description Contents of the PDR register may fail to be trans- ferred to memory during a DMA write operation when the falling edge of PEN or PWN aligns near the trail- ing edge of the output clock (CKO). If an external device overwrites the PDR, the DMA transaction is not completed. The status of the parallel data full (PDF) ﬂag and associated pin may be corrupted dur- ing this transaction. A DMA read transaction may fail if the falling edge of PEN or PGN aligns near the falling edge of CKO. The PDF ﬂag and associated pin may not correctly assume a deasserted state. The failure occurs only when the DSP operates at a clock frequency greater than 66 MHz, and CKO is asynchronous with respect to the PEN, PWN, and PGN signals. To eliminate this potential problem, a synchronous clocking scheme is needed. This clock- ing scheme prevents PEN, PWN and PGN from fall- ing a minimum of 3 ns before the falling edge of CKO. See Figure 2. Problem Resolution PEN, PWN, and PGN may be synchronized with the DSP clock to eliminate this potential alignment prob- lem. Figure 1 illustrates a circuit that may be used to synchronize these inputs. Figure 2 shows the associ- ated timing. The synchronization circuit delays the rise and fall points of PEN, PWN, and PGN. This added delay is equal to the maximum time of tCKOHCKOH + the cp to Q propagation delay of the F74 (tPLH or tPHL). For an 80 MHz CKI, the maximum delay would be 12.5 ns + the cp to Q delay of the F74. Subse- quently, the user must ensure that other timing speciﬁ- cations listed in Table 1 and Table 2 are not violated. 1 page Data Sheet Addendum November 1996 DSP32C Digital Signal Processor Timing Characteristics (continued) CKO VoM– VIH– PAB VIL– READ (PEN + PWN) VIM– VOH– PDB VOL– PDF1 VOM– PIF1 VOM– PDF2 VOM– PIF2 VOM– t91a t64 t66 t65 t70a DATA OUT t76g t67 READ OR WRITE t74 t75 t76a t76 Notes: PDF1 and PIF1 reﬂect the timing when PCR [10] = 0. PDF2 and PIF2 reﬂect the timing when PCR [10] = 1. Figure 4. PIO Timing—Read Cycle (PWN High) 5-3629 (C).b Table 2. Timing Characteristics for PIO Read Cycle (See Figure 4.) Abbreviated Reference t64 t65 t66 t67 t70a t74 t75 t76 t76a t76g t90a IEEE Symbol tPAVPRL tPRHPAX tPRLPDV tPRHPDZ tPRLPRH tPRLPDFL tPRLPIFL tPRHPIFL tPRHPDFL tPRWHPRWL tPGNLCKOL Parameter Address Setup Address Hold Access from Read Data Hold from Read Read Pulse PDF Read Delay PIF Read Delay PIF Read Delay PDF Read Delay PIO Idle† Read Setup 50 ns Min Max* 5— 0— — 17 27 2T — — 15 — 15 — T + 15 — T + 15 2T — 3— * T = tCKILCKIL (system clock period). † A minimum 2 x T interval is required for the start of the read or write cycle following the end of the previous read or write cycle. Lucent Technologies Inc. 5 5 Page Data Sheet June 1995 AT&T DSP32C Digital Signal Processor with External Memory Interface Description (continued) Table 2. Features and Benefits of the DSP32C Features Benefits Full 32-bit floating-point architecture Increased precision & dynamic range Simplifies program development to provide faster time to market Much easier algorithm development opens up new application possibilities Instruction started every instruction cycle Allows more complex functions or a greater num- ber of simultaneous functions to be implemented Four memory accesses per instruction cycle Exceptional memory bandwidth Eliminates memory accessing bottlenecks C-like assembly language Easy to learn/excellent readability Serial and parallel ports with DMA High bandwidth, nonintrusive I/O Clean interface to external devices Lower system cost Easy interface to PC buses External control via parallel I/O (PIO) Hardware data format conversions — IEEE* P754 floating-point — Integer conversions: 8-bit unsigned 16-bit linear 24-bit linear — µ-law/A-law conversions Eliminates lengthy software routines Permits shared data with host processor or other platforms Increased throughput in: — Graphics and image processing — Applications with 16-bit data — HQ digital audio and control applications — Telecom and speech applications Fully vectored interrupt structure with hardware Allows very fast interrupt processing (up to context save 2 million interrupts/s) Byte-addressable address space Efficient storage of 8- and 16-bit data Lower system cost Flexible wait-state facility — Each wait-state is 1/4 instruction cycle — Two independent external memory speed partitions Greater memory speed selection flexibility than conventional full-cycle wait-states Allows mixing of slow and fast memory Optimizes system speed/cost requirements * IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Table 3. DSP32C with External Memory Interface Device Speed Options Minimum Instruction Cycle Time (ns) Maximum Clock Frequency (MHz) 50 80.000 60 66.666 80 50.000 AT&T Microelectronics 3 11 Page

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