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PDF EUP2471JIR1 Data sheet ( Hoja de datos )
| Número de pieza | EUP2471JIR1 | |
| Descripción | 1.5A Dual WLED Flash Driver | |
| Fabricantes | Eutech Microelectronics | |
| Logotipo |  |
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EUP2471
1.5A Dual WLED Flash Driver
with I2C Compatible Interface
DESCRIPTION
The EUP2471 is a 2MHz fixed frequency, current mode
synchronous boost converter. The device is designed to
operate as a dual 750mA (1.5A total) constant current
driver for flash white LED application.
An industry-standard I2C serial digital input is used to
enable, disable and set the movie-mode current for each
flash LED with up to 16 movie-mode settings. The
EUP2471 also includes a separate Flash Enable input to
initiate both the flash operation and the default timer,
which can be used either to terminate a flash event at the
end of a user-programmed delay or as a safety feature.
The maximum flash and movie-mode current is set by
one external resistor; the ratio of Flash to Movie-mode
current is set at approximately 6.1:1.
An over-voltage protection feature keeps the output
voltage below the OVP threshold in case of an open LED
and an output short circuit protection limits the output
current during an output short to GND. The chip’s
quiescent current is less than 1.0µA in shutdown mode.
FEATUES
2.7V to 5.5V Input Supply Range
Dual Channel Output with Separate
Flash Enable
Up to 1.5A Regulated Output Current
(750mA per channel)
Up to 85% Efficiency
2 MHz Fixed Switching Frequency
I2C Compliant Serial Interface
- 400kHz Serial Transfer Rate
-16 Level Movie-mode Current
-Flash/Movie-mode
-Programmable LED Current
-Programmable Flash Safety Timer
True Load Disconnect
Input Current Limit
Output Over-Voltage, Short Circuit, and
Over-Temperature Protection
3mm × 3mm TDFN-14 Package
RoHS Compliant and 100% Lead (Pb)-Free
Halogen-Free
APPLICATIONS
Camera-enabled Cellular Phones
and Smart Phones
Digital Still Cameras (DSCs)
LED Photo Flash/Torch
Typical Application Circuit
DS2471 Ver1.0 Mar. 2011
Figure 1. EUP2471 Typical Application
1
1 page  
EUP2471Tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com
Electrical Characteristics (Continued)
VIN = 3.6V, CIN = 2.2µF, COUT = 2.2µF, L = 1µH, RSET = 107kΩ, TA = -40°C to 85°C, unless otherwise noted.
Typical values are at TA = 25°C.
Symbol
Parameter
Conditions
EUP2471
Min. Typ. Max.
I2C Control – SDA, SCL
tSU_DAT SDA Data Setup Time
tHD_DAT SDA Data Hold Time
100
0.9
tSU_STO
tBUF
Setup Time for STOP Condition
Bus Free Time between STOP and
START Condition
0.6
1.3
EN, FLEN Logic Control
VEN(L),
VFLEN(L)
VEN(H),
VFLEN(H)
tFLEN_OND
EN, FLEN Input Low Threshold
EN, FLEN Input High Threshold
FLEN ON Delay Time
EN= AGND
0.4
1.4
80
tFLEN_OFFD FLEN OFF Delay Time
EN= AGND
2
Unit
ns
µs
µs
µs
V
V
µs
µs
DS2471 Ver1.0 Mar. 2011
5
5 Page 
EUP2471Tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com
output current in both Flash and MM conditions. The I2C START and STOP Conditions
maximum movie-mode current level is set by
the maximum programmed flash current reduced
by the programmed flash-to-movie-mode ratio in
which the default value is 6.1:
START and STOP conditions are always generated by
the master. Prior to initiating a START, both the SDA
and SCL pins are in idle mode (idle mode is when there
is no activity on the bus and SDA and SCL are pulled
I MOVIE −MODE [A / B]
=
I FLOUT [A / B](MAX )
6.1
=
750 mA
6.1
≅ 120mA
high by the external pull-up resistors). A START
condition occurs when the master strobes the SDA line
low and after a short period strobes the SCL line low. A
To change the configuration or the settings, the
EUP2471 can be programmed via the I2C interface.
Triggering the FLEN low to high will enable a flash
event with the maximum flash current set by the RSET
resistor or with programmed flash current set
via the I2C interface. Concurrently, the flash
timer is also initiated. All data and register contents are
cleared (reset to the default value) after each flash event.
Flash Safety Timeout
The EUP2471 includes a timer circuit that enables the
flash current for a programmed period of time. This
feature eliminates the need for an external, housekeeping
baseband controller to contain a safety delay routine. It
also serves as a protection feature to minimize thermal
issues with the flash LEDs in the event an external
controller’s flash software routine experiences hang-up
or freeze. The flash safety timeout, T can be calculated
by the following equation:
T = 7.98s/µF · CT
Where T is in seconds and CT is the capacitance of the
timer capacitor in µF.
For example, using a 47nF capacitor for CT sets the flash
timeout to:
START condition acts as a signal to all ICs that
transmission activity is about to occur on the I2C bus. A
STOP condition, as shown in Figure 4, is when master
releases the bus and SCL changes from low to high
followed by SDA low-to- high transition. The master
does not issue an ACKNOWLEDGE and releases the
SCL and SDA pins.
I2C Address Bit Map
Figure5 illustrates the address bit transfer. The 7-bit
address is transferred with the Most Significant Bit
(MSB) first and is valid when SCL is high. This is
followed by the R/W bit in the Least Significant Bit
(LSB) location. The R/W bit on the eighth bit determines
the direction of the transfer (a '1' for read or a '0' for
write). The EUP2471 is a write-only device and the R/W
bit must be set low. The Acknowledge bit (ACK) is set
to low by the EUP2471 to acknowledge receipt of the
address.
I2C Register Address/Data Bit Map
Figure 6 illustrates the Register Address or the serial data
bit transfer. The 8-bit data is always transferred most
significant bit first and is valid when SCL is high. The
Acknowledge bit (ACK) is set low by the EUP2471 to
acknowledge receipt of the register address or the data.
Flash Safety Timeout = 7.98s/µF · 0.047µF = 375ms
I2C Acknowledge Bit (ACK)
The Acknowledge bit is the ninth bit of each transfer on
The relationship between the flash safety timeout and the
capacitance of the timer capacitor is illustrated in Flash
Timeout Delay VS CT Capacitance.
I2C Serial Interface
The EUP2471 is fully compliant with the industry-stan-
dard I2C interface. The I2C two-wire communications bus
the SDA line. It is used to send back a confirmation to
the master that the data has been received properly by the
target device. For each ACK to take place, the master
must first release the SDA line, and then the target
device will pull the SDA line low, as shown in Figures 3,
5, and 6.
consists of SDA and SCL lines. SDA provides data,
while SCL provides clock synchronization with speed up
to 400kHz. SDA data transfers device address followed
by a register address and data bits sequence. When
using the I2C interface, EN is pulled high to enable the
device or low to disable the device. The I2C serial
interface requires a master to initiate all the
communications with target devices. The EUP2471 is a
target device and only supports the write protocol. The
EUP2471 is manufactured with a target device address
of 0 × 37 (Hex). See Figure 3 for the I2C interface
diagram.
DS2471 Ver1.0 Mar. 2011
11
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet EUP2471JIR1.PDF ] | |
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