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PDF LTC3350 Data sheet ( Hoja de datos )
| Número de pieza | LTC3350 | |
| Descripción | High Current Supercapacitor Backup Controller and System Monitor | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Features
Electrical Specifications Subject to Change
LTC3350
High Current Supercapacitor
Backup Controller and
System Monitor
Description
n High Efficiency Synchronous Step-Down CC/CV
Charging of One to Four Series Supercapacitors
n Step-Up Mode in Backup Provides Greater
Utilization of Stored Energy in Supercapacitors
n 14-Bit ADC for Monitoring System Voltages/Currents,
Capacitance and ESR
n Active Overvoltage Protection Shunts
n Internal Active Balancers—No Balance Resistors
n VIN: 4.5V to 35V, VCAP(n): Up to 5V per Capacitor,
Charge/Backup Current: 10+A
n Programmable Input Current Limit Prioritizes System
Load Over Capacitor Charge Current
n Dual Ideal Diode PowerPath™ Controller
n All N-FET Charger Controller and PowerPath Controller
n Compact 38-Lead 5mm × 7mm QFN Package
Applications
n High Current 12V Ride-Through UPS
n Servers/Mass Storage/High Availability Systems
The LTC®3350 is a backup power controller that can charge
and monitor a series stack of one to four supercapacitors.
The LTC3350’s synchronous step-down controller drives
N‑channel MOSFETs for constant current/constant voltage
charging with programmable input current limit. In addition,
the step-down converter can run in reverse as a step-up
converter to deliver power from the supercapacitor stack
to the backup supply rail. Internal balancers eliminate the
need for external balance resistors and each capacitor has
a shunt regulator for overvoltage protection.
The LTC3350 monitors system voltages, currents, stack
capacitance and stack ESR which can all be read over
the I2C/SMBus. The dual ideal diode controller uses
N-channel MOSFETs for low loss power paths from the
input and supercapacitors to the backup system supply.
The LTC3350 is available in a low profile 38-lead 5mm ×
7mm × 0.75mm QFN surface mount package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Patents pending.
Typical Application
High Current Supercapacitor Charger and Backup Supply
ICHG (STEP-DOWN)
VIN
INFET VOUTSP VOUTSN
PFI OUTFB
IBACKUP
VOUT
Backup Operation
PBACKUP = 25W
OUTFET
TGATE
SW
BGATE
LTC3350
ICAP
VCAP
I2C CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
VCAP < VOUT
(STEP-UP)
VCAP > VOUT
(DIRECT
CONNECT)
10F VCAP
10F
10F
10F
3350 TA01a
VOUT
2V/DIV
VCAP
2V/DIV
VIN
2V/DIV
0V
400ms/DIV
BACK PAGE APPLICATION CIRCUIT
For more information www.linear.com/LTC3350
3350 TA01a
3350p
1
1 page  
LTC3350
E lectrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = 12V, VDRVCC = VINTVCC unless otherwise
noted.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX
DCMAX
Maximum Duty Cycle
Step-Down Mode
Step-Up Mode
97 98 99.5
87 93
Gate Drivers
RUP-TG
TGATE Pull-Up On-Resistance
RDOWN-TG TGATE Pull-Down On-Resistance
RUP-BG
BGATE Pull-Up On-Resistance
RDOWN-BG BGATE Pull-Down On-Resistance
tr-TG TGATE 10% to 90% Rise Time
tf-TG TGATE 10% to 90% Fall Time
tr-BG BGATE 10% to 90% Rise Time
tf-BG BGATE 10% to 90% Fall Time
tNO Non-Overlap Time
tON(MIN)
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
∆VINTVCC Load Regulation
PowerPath/Ideal Diodes
CLOAD = 3.3nF
CLOAD = 3.3nF
CLOAD = 3.3nF
CLOAD = 3.3nF
5.2V ≤ VIN ≤ 35V
IINTVCC = 50mA
2
0.6
2
0.6
18 25
8 15
18 25
8 15
50
85
5
–1.5 –2.5
VFTO Forward Turn-On Voltage
VFR Forward Regulation
VRTO Reverse Turn Off
tIF(ON)
INFET Rise Time
tIF(OFF)
INFET Fall Time
tOF(ON)
OUTFET Rise Time
tOF(OFF)
OUTFET Fall Time
Power-Fail Comparator
INFET – VIN > 3V, CINFET = 3.3nF
INFET – VIN < 1V, CINFET = 3.3nF
OUTFET – VCAP > 3V, COUTFET = 3.3nF
OUTFET – VCAP < 1V, COUTFET = 3.3nF
65
30
–30
560
1.5
0.13
0.26
VPFI(TH)
VPFI(HYS)
IPFI
VPFO
IPFO
PFI Input Threshold (Falling Edge)
PFI Hysteresis
PFI Input Leakage Current
PFO Output Low Voltage
PFO High-Z Leakage Current
PFI Falling to PFO Low Delay
VPFI = 0.5V
ISINK = 5mA
VPFO = 5V
20mV of Overdrive on PFI
l 1.147 1.17 1.193
30
l –50
50
200
l1
85
PFI Rising to PFO High Delay
20mV of Overdrive on PFI
0.4
CAPGD
VCAPFB(TH) CAPGD Rising Threshold as % of Regulated VCAP Vcapfb_dac = Full Scale (1111b)
Feedback Voltage
l 90 92 94
VCAPFB(HYS)
VCAPGD
ICAPGD
CAPGD Hysteresis at CAPFB as a % of Regulated
VCAP Feedback Voltage
CAPGD Output Low Voltage
CAPGD High-Z Leakage Current
Vcapfb_dac = Full Scale (1111b)
ISINK = 5mA
VCAPGD = 5V
l
1.25
200
1
UNITS
%
%
Ω
Ω
Ω
Ω
ns
ns
ns
ns
ns
ns
V
%
mV
mV
mV
µs
µs
µs
µs
V
mV
nA
mV
μA
ns
μs
%
%
mV
μA
For more information www.linear.com/LTC3350
3350p
5
5 Page 
LTC3350
Pin Functions
OUTFET (Pin 20): Output Ideal Diode Gate Drive Out-
put. This pin controls the gate of an external N-channel
MOSFET used as an ideal diode between VOUT and VCAP.
The gate drive receives power from the internal charge
pump output VCAPP5. The source of the N-channel
MOSFET should be connected to VCAP and the drain should
be connected to VOUTSN. If the output ideal diode MOSFET
is not used, OUTFET should be left floating.
VCAP (Pin 21): Supercapacitor Stack Voltage and Charge
Current Sense Amplifier Negative Input. Connect this pin
to the top of the supercapacitor stack. The voltage at this
pin is digitized and can be read in the meas_vcap register.
ICAP (Pin 22): Charge Current Sense Amplifier Positive
Input. The ICAP and VCAP pins measure the voltage across
the sense resistor, RSNSC, to provide instantaneous cur-
rent signals for the control loops and ESR measurement
system. The maximum charge current is 32mV/RSNSC.
VCC2P5 (Pin 23): Internal 2.5V Regulator Output. This
regulator provides power to the internal logic circuitry.
Decouple this pin to ground with a minimum 1μF low ESR
tantalum or ceramic capacitor.
SW (Pin 24): Switch Node Connection to the Inductor.
The negative terminal of the boot-strap capacitor, CB, is
connected to this pin. The voltage on this pin is also used
as the source reference for the top side N-channel MOS-
FET gate drive. In step-down mode, the voltage swing on
this pin is from a diode (external) forward voltage below
ground to VOUT. In step-up mode the voltage swing is from
ground to a diode forward voltage above VOUT.
TGATE (Pin 25): Top Gate Driver Output. This pin is the
output of a floating gate driver for the top external N‑channel
MOSFET. The voltage swing at this pin is ground to VOUT
+ DRVCC.
BST (Pin 26): TGATE Driver Supply Input. The positive
terminal of the boot-strap capacitor, CB, is connected to
this pin. This pin swings from a diode voltage drop below
DRVCC up to VOUT + DRVCC.
BGATE (Pin 27): Bottom Gate Driver Output. This pin
drives the bottom external N-channel MOSFET between
PGND and DRVCC.
DRVCC (Pin 28): Power Rail for Bottom Gate Driver. Con-
nect to INTVCC or to an external supply. Decouple this pin
to ground with a minimum 2.2μF low ESR tantalum or
ceramic capacitor. Do not exceed 5.5V on this pin.
INTVCC (Pin 29): Internal 5V Regulator Output. The control
circuits and gate drivers (when connected to DRVCC) are
powered from this supply. If not connected to DRVCC,
decouple this pin to ground with a minimum 1μF low ESR
tantalum or ceramic capacitor.
VOUTSN (Pin 30): Input Current Limiting Amplifier Nega-
tive Input. A sense resistor, RSNSI, between VOUTSP and
VOUTSN sets the input current limit. The maximum input
current is 32mV/RSNSI. An RC network across the sense
resistor can be used to modify loop compensation. To
disable input current limit, connect this pin to VOUTSP.
VOUTSP (Pin 31): Backup System Supply Voltage and
Input Current Limiting Amplifier Positive Input. The voltage
across the VOUTSP and VOUTSN pins are used to regulate
input current. This pin also serves as the power supply
for the IC. The voltage at this pin is digitized and can be
read in the meas_vout register.
VOUTM5 (Pin 32): VOUT – 5V Regulator. This pin is regu-
lated to 5V below VOUT or to ground if VOUT < 5V. This
rail provides power to the input current sense amplifier.
Decouple this pin with at least 1μF to VOUT.
INFET (Pin 33): Input Ideal Diode Gate Drive Output. This
pin controls the gate of an external N-channel MOSFET
used as an ideal diode between VIN and VOUT. The gate
drive receives power from an internal charge pump. The
source of the N-channel MOSFET should be connected
to VIN and the drain should be connected to VOUTSP. If
the input ideal diode MOSFET is not used, INFET should
be left floating.
VIN (Pin 34): External DC Power Source Input. Decouple
this pin with at least 0.1μF to ground. The voltage at this
pin is digitized and can be read in the meas_vin register.
CAP_SLCT0, CAP_SLCT1 (Pins 35, 36): CAP_SLCT0 and
CAP_SLCT1 set the number of super-capacitors used.
Refer to Table 1 in the Applications Information section.
For more information www.linear.com/LTC3350
3350p
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3350.PDF ] | |
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