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PDF AT42QT1060 Data sheet ( Hoja de datos )
| Número de pieza | AT42QT1060 | |
| Descripción | 6-channel Sensor IC | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Configurations:
– Can be configured as a combination of keys and input/output lines
• Number of Keys:
– 2 to 6
• Number of I/O Lines:
– 7, configurable for input or output, with PWM control for LED driving
• Technology:
– Patented spread-spectrum charge-transfer (direct mode)
• Key Outline Sizes:
– 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and
shapes possible
• Layers Required:
– One
• Electrode Materials:
– Etched copper
– Silver
– Carbon
– Indium Tin Oxide (ITO)
• Panel Materials:
– Plastic
– Glass
– Composites
– Painted surfaces (low particle density metallic paints possible)
• Panel Thickness:
– Up to 10 mm glass (electrode size dependent)
– Up to 5 mm plastic (electrode size dependent)
• Key Sensitivity:
– Individually settable via simple commands over serial interface
• Interface:
– I2C-compatible slave mode (100 kHz). Discrete detection outputs
• Power:
– 1.8V to 5.5V
• Package:
– 28-pin 4 x 4 mm MLF RoHS compliant IC
• Signal Processing:
– Self-calibration
– auto drift compensation
– noise filtering
– Adjacent Key Suppression™
• Applications:
– Mobile appliances
QTouch™
6-channel
Sensor IC
AT42QT1060
9505E–AT42–02/09
1 page  
AT42QT1060
2. Overview
2.1 Introduction
The AT42QT1060 (QT1060) is a digital burst mode charge-transfer (QT™) capacitive sensor
driver designed specifically for mobile phone applications. The device can sense from two to six
keys; up to four keys can be disabled by not installing their respective sense capacitors (Cs). It
also has up to seven configurable input/output lines, with Pulse Width Modulation (PWM) for
LED driving.
This device includes all signal processing functions necessary to provide stable sensing under a
wide variety of changing conditions, and the outputs are fully debounced. Only a few external
parts are required for operation.
The QT1060 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the
effects of external noise, and to suppress RF emissions.
2.2 Keys
The QT1060 can have a minimum of two keys and a maximum of six keys. These can be
constructed in different shapes and sizes. See “Features” on page 1 for the recommended
dimensions.
Unused keys should be disabled by removing the corresponding Cs and Rs components and
connecting the SNS pins as shown in the “If Unused” column of Table 1-1 on page 2. The
unused keys are always pared from the burst sequence in order to optimize speed. See
Section 7. on page 25 about setting up the keys.
2.3 Standalone Mode
The QT1060 can operate in a standalone mode where an I2C-compatible interface is not
required. To enter standalone mode, connect SDA to Vss and SCL to Vdd before powering up
the QT1060.
In standalone mode the default start-up values are used except for the I/O mask (Address 23).
The I/O mask is configured so that all the IOs are outputs (IO mask = 0x7F). This means that
key detection is reported via their respective IOs.
2.4 I/O Lines
2.4.1
Overview
There is an input/output (I/O) port consisting of seven lines that can be individually programmed
as inputs or outputs. They can be either a digital type or PWM. The PWM level can be set to 256
possible values and is common to all lines.
The I/O lines are normally initialized as inputs. However, if an I2C-compatible interface is not
used and the SDA and SCL pins are connected to Vss and Vdd respectively, then the I/O lines
are initialized as outputs (see Section 2.3).
The outputs can also be linked to either the detection channels or the output register to allow the
outputs to be either user controlled or to indicate detection. These options can be set in the pin
control masks (see Table 6-1 on page 17).
Unused I/O lines should be disabled by connecting as shown in the “If Unused” column of
Table 1-1 on page 2. See Section 7. on page 25 about setting up the I/O lines.
9505E–AT42–02/09
5
5 Page 
AT42QT1060
4. I2C-compatible Bus Operation
4.1 Interface Bus
More detailed information about the I2C-compatible bus protocol is available from
www.i2C-bus.org. Devices are connected onto the I2C-compatible bus as shown in Figure 4-1.
Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I2C-compatible
devices must be open-drain type. This implements a wired-AND function which allows any and
all devices to drive the bus, one at a time. A low level on the bus is generated when a device
outputs a zero.
Figure 4-1. I2C-compatible Interface Bus
Vdd
Device 1 Device 2 Device 3
Device n R1
R2
SDA
SCL
Table 4-2. I2C-compatible Bus Specifications
Parameter
Address space
Maximum bus speed (SCL)
Hold time START condition
Setup time for STOP condition
Bus free time between a STOP and START condition
Rise times on SDA and SCL
Unit
7-bit
100 kHz
4 µs minimum
4 µs minimum
4.7 µs minimum
1 µs maximum
4.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the
data line must be stable when the clock line is high; The only exception to this rule is for
generating START and STOP conditions.
9505E–AT42–02/09
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT42QT1060.PDF ] | |
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