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PDF MB85RC256V Data sheet ( Hoja de datos )
| Número de pieza | MB85RC256V | |
| Descripción | 256K (32K x 8)Bit I2C | |
| Fabricantes | Fujitsu | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
Memory FRAM
256 K (32 K × 8) Bit I2C
MB85RC256V
DS501-00017-0v01-E
■ DESCRIPTION
The MB85RC256V is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768
words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
Unlike SRAM, the MB85RC256V is able to retain data without using a data backup battery.
The read/write endurance of the nonvolatile memory cells used for the MB85RC256V has improved to be
at least 1010 cycles, significantly outperforming other nonvolatile memory products in the number.
The MB85RC256V does not need a polling sequence after writing to the memory such as the case of Flash
memory or E2PROM.
■ FEATURES
• Bit configuration
: 32,768 words × 8 bits
• Two-wire serial interface
: Fully controllable by two ports: serial clock (SCL) and serial data (SDA).
• Operating frequency
: 2.7V to 4.5V 400 kHz (Max)
4.5V to 5.5V 1 MHz (Max)
• Read/write endurance
: 1010 times / byte
• Data retention
: 10 years ( + 70 °C)
• Operating power supply voltage : 2.7 V to 5.5 V
• Low-power consumption
: Operating power supply current TBD μA (Typ @1 MHz)
Standby current TBD μA (Typ)
• Operation ambient temperature range
: − 40 °C to + 85 °C
• Package
: 8-pin plastic SOP (FPT-8P-M02)
8-pin plastic SOP (FPT-8P-M08)
Both are RoHS compliant
Copyright©2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.7
1 page  
MB85RC256V
■ ACKNOWLEDGE (ACK)
In the I2C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge
signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually
outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully transmitted and
received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow
the acknowledge signal to be received and checked. During this Hi-Z released period, the receiver side pulls
the SDA line down to indicate the “L” level that the previous 8 bits communication is successfully received.
In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side
stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state
after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition
in this released bus state.
• Acknowledge timing overview diagram
SCL
123
89
SDA
Start
The transmitter side should always release SDA on the
9th bit. At this time, the receiver side outputs a pull-down
if the previous 8 bits data are received correctly (ACK re-
sponse).
ACK
DS501-00017-0v01-E
5
5 Page 
MB85RC256V
■ SOFTWARE RESET SEQUENCE OR COMMAND RETRY
In case the malfunction has occurred after power on, the master side stopped the I2C communication during
processing, or unexpected malfunction has occurred, execute the following (1) software recovery sequence
just before each command, or (2) retry command just after failure of each command.
(1) Software Reset Sequence
Since the slave side may be outputting “L” level, do not force to drive “H” level, when the master side drives
the SDA port. This is for preventing a bus conflict. The additional hardware is not necessary for this software
reset sequence.
9 set of “Start Conditions and one “1” data”
SCL
SDA
Hi-Z state by pull up Resistor
Send “Start Condition and one data “1”” .
Repeat these 9 times just before Write or Read command.
(2) Command Retry
Command retry is useful to recover from failure response during I2C communication.
DS501-00017-0v01-E
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB85RC256V.PDF ] | |
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