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PDF ADP3650 Data sheet ( Hoja de datos )
| Número de pieza | ADP3650 | |
| Descripción | 12V MOSFET Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anti-crossconduction protection circuitry
OD for disabling the driver outputs
APPLICATIONS
Telecom and datacom networking
Industrial and medical systems
Point of load conversion: memory, DSP, FPGA, ASIC
Dual, Bootstrapped, 12 V MOSFET
Driver with Output Disable
ADP3650
GENERAL DESCRIPTION
The ADP3650 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, the two switches in a
nonisolated synchronous buck power converter. Each driver is
capable of driving a 3000 pF load with a 45 ns propagation delay
and a 25 ns transition time. One of the drivers can be boot-
strapped and is designed to handle the high voltage slew rate
associated with floating high-side gate drivers. The ADP3650
includes overlapping drive protection to prevent shoot-through
current in the external MOSFETs.
The OD pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
The ADP3650 is specified over the temperature range of −40°C
to +85°C and is available in 8-lead SOIC_N and 8-lead LFCSP_VD
packages.
FUNCTIONAL BLOCK DIAGRAM
12V
ADP3650
IN 2
VCC
4
DELAY
LATCH
R1
R2 Q
S
OD 3
CMP
1V
DELAY
CMP
VCC
6
CONTROL
LOGIC
Figure 1.
D1
BST
1
CBST1
DRVH
8
CBST2
RG
Q1
SW
7
RBST
TO
INDUCTOR
DRVL
5
PGND
6
Q2
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
All voltages are referenced to PGND, unless otherwise noted.
Table 2.
Parameter
VCC
BST
DC
<200 ns
BST to SW
SW
DC
<200 ns
DRVH
DC
<200 ns
DRVL
DC
<200 ns
IN, OD
Operating Ambient Temperature Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +15 V
−0.3 V to VCC + 15 V
−0.3 V to +35 V
−0.3 V to +15 V
−5 V to +15 V
−10 V to +25 V
SW − 0.3 V to BST + 0.3 V
SW − 2 V to BST + 0.3 V
−0.3 V to VCC + 0.3 V
−2 V to VCC + 0.3 V
−0.3 V to +6.5 V
−40°C to +85°C
0°C to 150°C
−65°C to +150°C
300°C
215°C
260°C
ADP3650
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
8-Lead SOIC_N (R-8)
2-Layer Board
4-Layer Board
8-Lead LFCSP_VD1 (CP-8-2)
4-Layer Board
θJA Unit
123 °C/W
90 °C/W
50 °C/W
1 For LFCSP_VD, θJA is measured per JEDEC STD with exposed pad soldered to PCB.
ESD CAUTION
Rev. A | Page 5 of 12
5 Page 
The MOSFET vendor should provide a safe operating rating for
maximum voltage slew rate at a given drain current. This allows
the designer to derate for the FET turn-off condition described
in this section. When this specification is obtained, determine
the maximum current expected in the MOSFET by
( )I MAX = I DC (per phase) + VCC −VOUT
× D MAX (5)
f MAX × LOUT
where:
DMAX is determined by the voltage controller being used with
the driver. This current is divided roughly equally between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin).
LOUT is the output inductor value.
When producing the design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as in the PCB. However, it can be measured to
determine whether it is safe. If it appears that the dV/dt is too
fast, an optional gate resistor can be added between DRVH and
the high-side MOSFETs. This resistor slows down the dV/dt,
but it increases the switching losses in the high-side MOSFETs.
The ADP3650 is optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently, yet minimizes dV/dt. However, some high speed
MOSFETs may require this external gate resistor depending on
the currents being switched in the MOSFET.
LOW-SIDE (SYNCHRONOUS) MOSFETS
The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies a
large input gate capacitance and gate charge. The first concern is
to make sure that the power delivery from the ADP3650 DRVL
does not exceed the thermal rating of the driver.
The next concern for the low-side MOSFETs is to prevent
them from being inadvertently switched on when the high-side
MOSFET turns on. This occurs due to the drain-gate capacitance
(Miller capacitance, also specified as Crss) of the MOSFET. When
the drain of the low-side MOSFET is switched to VCC by the
high-side MOSFET turning on (at a dV/dt rate), the internal
gate of the low-side MOSFET is pulled up by an amount roughly
equal to VCC × (Crss/Ciss). It is important to make sure that this
does not put the MOSFET into conduction.
Another consideration is the nonoverlap circuitry of the
ADP3650 that attempts to minimize the nonoverlap period.
During the state of the high-side MOSFET turning off to the
low-side MOSFET turning on, the SW pin is monitored (as well
as the conditions of SW prior to switching) to adequately
prevent overlap.
ADP3650
However, during the low-side turn-off to high-side turn-on,
the SW pin does not contain information for determining
the proper switching time, so the state of the DRVL pin is
monitored to go below one-sixth of VCC; then, a delay is added.
Due to the Miller capacitance and internal delays of the low-
side MOSFET gate, ensure that the Miller-to-input capacitance
ratio is low enough, and that the low-side MOSFET internal
delays are not so large as to allow accidental turn-on of the
low-side MOSFET when the high-side MOSFET turns on.
PCB LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards. Figure 15 shows an example of the typical land
patterns based on these guidelines.
• Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
• Minimize trace inductance between the DRVH and DRVL
outputs and the MOSFET gates.
• Connect the PGND pin of the ADP3650 as close as
possible to the source of the lower MOSFET.
• Locate the VCC bypass capacitor as close as possible to
the VCC and PGND pins.
• When possible, use vias to other layers to maximize
thermal conduction away from the IC.
CBST1
CBST2
RBST
D1
CVCC
Figure 15. External Component Placement Example
Rev. A | Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADP3650.PDF ] | |
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