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PDF ISL6622 Data sheet ( Hoja de datos )
| Número de pieza | ISL6622 | |
| Descripción | VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
VR11.1 Compatible Synchronous
Rectified Buck MOSFET Drivers
The ISL6622 is a high frequency MOSFET driver designed to
drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. The advanced
PWM protocol of ISL6622 is specifically designed to work
with Intersil VR11.1 controllers and combined with
N-Channel MOSFETs, form a complete core-voltage regulator
solution for advanced microprocessors. When ISL6622
detects a PSI protocol sent by an Intersil VR11.1 controller, it
activates Diode Emulation (DE) and Gate Voltage
Optimization Technology (GVOT) operation; otherwise, it
operates in normal Continuous Conduction Mode (CCM)
PWM mode.
In the 8 Ld SOIC package, the ISL6622 drives the upper and
lower gates to VCC during normal PWM mode, while the
lower gate drops down to a fixed 5.75V (typically) during PSI
mode. The 10 Ld DFN part offers more flexibility: the upper
gate can be driven from 5V to 12V via the UVCC pin, while the
lower gate has a resistor-selectable drive voltage of 5.75V,
6.75V, and 7.75V (typically) during PSI mode. This provides
the flexibility necessary to optimize applications involving
trade-offs between gate charge and conduction losses.
To further enhance light load efficiency, the ISL6622 enables
diode emulation operation during PSI mode. This allows
Discontinuous Conduction Mode (DCM) by detecting when
the inductor current reaches zero and subsequently turning
off the low side MOSFET to prevent it from sinking current.
An advanced adaptive shoot-through protection is integrated
to prevent both the upper and lower MOSFETs from
conducting simultaneously and to minimize dead time. The
ISL6622 has a 20kΩ integrated high-side gate-to-source
resistor to prevent self turn-on due to high input bus dV/dt.
This driver also has an overvoltage protection feature
operational while VCC is below the POR threshold: the
PHASE node is connected to the gate of the low side
MOSFET (LGATE) via a 10kΩ resistor, limiting the output
voltage of the converter close to the gate threshold of the low
side MOSFET, dependent on the current being shunted,
which provides some protection to the load should the upper
MOSFET(s) become shorted.
ISL6622
October 30, 2008
FN6470.2
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-through Protection
• Integrated LDO for Selectable Lower Gate Drive Voltage
(5.75V, 6.75V, 7.75V) to Optimize Light Load Efficiency
• 36V Internal Bootstrap Diode
• Advanced PWM Protocol (Patent Pending) to Support PSI
Mode, Diode Emulation, Three-State Operation
• Diode Emulation for Enhanced Light Load Efficiency
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Integrated High-Side Gate-to-Source Resistor to Prevent
from Self Turn-On due to High Input Bus dV/dt
• Pre-POR Overvoltage Protection for Start-up and
Shutdown
• Power Rails Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free (RoHS Compliant)
Applications
• High Light Load Efficiency Voltage Regulators
• Core Regulators for Advanced Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck
Regulators” for Power Train Design, Layout Guidelines,
and Feedback Compensation Design
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6622
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Three-State Upper Gate Falling Threshold (Note 4)
VCC = 12V
- 2.8 -
V
UGATE Rise Time (Note 4)
tRU VVCC = 12V, 3nF Load, 10% to 90% - 26 -
LGATE Rise Time (Note 4)
tRL VVCC = 12V, 3nF Load, 10% to 90% - 18 -
UGATE Fall Time (Note 4)
tFU VVCC = 12V, 3nF Load, 90% to 10% - 18 -
LGATE Fall Time (Note 4)
tFL
VVCC = 12V, 3nF Load, 90% to 10%
-
12
-
UGATE Turn-On Propagation Delay (Note 4)
tPDHU VVCC = 12V, 3nF Load, Adaptive
- 20 -
LGATE Turn-On Propagation Delay (Note 4)
tPDHL VVCC = 12V, 3nF Load, Adaptive
- 10 -
UGATE Turn-Off Propagation Delay (Note 4)
tPDLU VVCC = 12V, 3nF Load
- 10 -
LGATE Turn-Off Propagation Delay (Note 4)
tPDLL
VVCC = 12V, 3nF Load
- 10 -
Diode Braking Holdoff Time (Note 4)
tUG_OFF_DB VVCC = 12V
- 60 -
Minimum LGATE ON-Time At Diode Emulation
tLG_ON_DM VVCC = 12V
230 330 450
OUTPUT (Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
IU_SOURCE VVCC = 12V, 3nF Load
RU_SOURCE 20mA Source Current
IU_SINK VVCC = 12V, 3nF Load
RU_SINK 20mA Sink Current
IL_SOURCE VVCC = 12V, 3nF Load
RL_SOURCE 20mA Source Current
IL_SINK VVCC = 12V, 3nF Load
RL_SINK 20mA Sink Current
- 1.25 -
- 2.0 -
- 2-
- 1.35 -
- 2-
- 1.35 -
- 3-
- 0.90 -
A
Ω
A
Ω
A
Ω
A
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 8 for guidance in choosing the capacitor value.
- 3 GD_SEL This pin sets the LG drive voltage in PSI mode.
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation,
see the three-state PWM Input section on page 6 for further details. Connect this pin to the PWM output of the
controller.
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 LVCC This pin provides power for the LGATE drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
- 8 UVCC This pin provides power to the upper gate drive. Its operating range is +5V to 12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
7 9 VCC Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC and to the LDO for the
lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
- 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5 FN6470.2
October 30, 2008
5 Page 
ISL6622
Dual Flat No-Lead Plastic Package (DFN)
2X
AD
0.15 C A
2X
0.15 C B
6
INDEX
AREA
TOP VIEW
E
B
C
SEATING
PLANE
SIDE VIEW
0.10 C
A
0.08 C
A3
78
(DATUM B)
D2
6
INDEX
AREA
(DATUM A)
D2/2
12
NX k
E2
E2/2
NX L
8
N N-1
e
(Nd-1)Xe
REF.
BOTTOM VIEW
NX b
5
0.10 M C A B
NX (b)
5
(A1)
SECTION "C-C"
0.415
0.200 NX L
NX b
C
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN NOMINAL MAX
NOTES
A 0.80 0.90 1.00
-
A1
-
- 0.05
-
A3 0.20 REF -
b 0.18 0.23 0.28
5,8
D
3.00 BSC
-
D2 1.95 2.00 2.05
7,8
E
3.00 BSC
-
E2 1.55 1.60 1.65
7,8
e
0.50 BSC
-
k 0.25 - - -
L 0.30 0.35 0.40
8
N 10 2
Nd 5 3
NOTES:
Rev. 3 6/04
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
CL
L
e
CC
TERMINAL TIP
FOR ODD TERMINAL/SIDE
11 FN6470.2
October 30, 2008
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL6622.PDF ] | |
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