|
|
PDF HD74ALVCH16831 Data sheet ( Hoja de datos )
| Número de pieza | HD74ALVCH16831 | |
| Descripción | 1-to 4 Address Register / Driver with 3-state Outputs | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HD74ALVCH16831 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
HD74ALVCH16831
1-to 4 Address Register / Driver with 3-state Outputs
ADE-205-194 (Z)
Preliminary
1st. Edition
March 1998
Description
This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal
for use in applications in which a single address bus is driving four separate memory locations. The
HD74ALVCH16831 can be used as a buffer or a register, depending on the logic level of the select (SEL)
input. When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are
controlled by the two output enable (OE) controls. Each OE controls two groups of nine outputs. When
SEL is logic low, the device is in the register mode. The register is an edge triggered D-type flip flop. On
the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers.
OE controls operate the same as in buffer mode. When OE is logic low, the outputs are in a normal logic
state (high or low logic level). When OE is logic high, the outputs are in the high impedance state. To
ensure the high impedance state during power up or power down, OE should be tied to VCC through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver. SEL and OE do not affect the internal operation of the flip flops. Old data can be retained or new
data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided
to hold unused or floating data inputs at a valid logic level.
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
1 page  
Logic Diagram
OE1 20
OE2 21
CLK 19
A1 8
SEL 22
CLK
DQ
HD74ALVCH16831
5 1Y1
4 2Y1
2 3Y1
1 4Y1
To eight other channels
5
5 Page 
Package Dimensions
17.10 Max
80 41
1
0.23 Max
0.40
0.07 M
40
0.08
HD74ALVCH16831
Unit : mm
8.40 Max
12° Max
0.75 Max
Hitachi code
EIAJ code
JEDEC code
—
—
—
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HD74ALVCH16831.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HD74ALVCH16830 | 1-bit to 2-bit Address Driver with 3-state Outputs | Hitachi Semiconductor |
| HD74ALVCH16831 | 1-to 4 Address Register / Driver with 3-state Outputs | Hitachi Semiconductor |
| HD74ALVCH16835 | 18-bit Universal Bus Driver with 3-state Outputs | Hitachi Semiconductor |
| HD74ALVCH16836 | 20-bit Universal Bus Driver with 3-state Outputs | Hitachi Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |