PDF SGN02G72F1BQ1SA-DCRT Data sheet ( Hoja de datos )

Número de pieza	SGN02G72F1BQ1SA-DCRT
Descripción	204 Pin ECC SO-DIMM
Fabricantes	Swissbit
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Data Sheet Rev.1.0 16.09.2013 2048MB DDR3 – SDRAM ECC SO-UDIMM 204 Pin ECC SO-DIMM SGN02G72F1BQ1SA-xx[E/W]RT 2GByte in FBGA Technology RoHS compliant Options:  Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1600 MT/s CL11 Marking -CC -DC  Module density 2GByte with 9 dies and 1 rank  Standard Grade Grade E Grade W (TA) 0°C to 70°C (TC) 0°C to 85°C (TA) 0°C to 85°C (TC) 0°C to 95°C (TA) -40°C to 85°C (TC) -40°C to 95°C ) The refresh rate has to be doubled when 85°C<TC<95°C) Environmental Requirements:  Operating temperature (ambient) Standard Grade 0°C to 70°C E-Grade 0°C to 85°C W-Grade  Operating Humidity -40°C to 85°C 10% to 90% relative humidity, noncondensing  Operating Pressure 105 to 69 kPa (up to 10000 ft.)  Storage Temperature -55°C to 100°C  Storage Humidity 5% to 95% relative humidity, noncondensing  Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C Features:  204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double Data Rate synchronous DRAM Module  Module organization: single rank 256M x 72  VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V  1.5V I/O ( SSTL_15 compatible)  Fly-by-bus with termination for C/A & CLK bus  On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM  Gold-contact pad  This module is fully pin and functional compatible to the JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM design spec. and JEDEC- Standard MO-268. (see www.jedec.org)  The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)]  DDR3 - SDRAM component Samsung K4B2G0846Q-BYK0  256Mx8 DDR3 SDRAM in PG-TFBGA-78 package  8-bit prefetch architecture  Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type.  On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity.  Refresh, Self Refresh and Power Down Modes.  ZQ Calibration for output driver and ODT.  System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern. Figure: mechanical dimensions1 Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 1if no tolerances specified ± 0.15mm www.swissbit.com eMail: [email protected] Page 1 of 16 1 page Data Sheet Rev.1.0 16.09.2013 FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR3 SDRAM SO-UDIMM, 1 RANK AND 9 COMPONENTS DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS8 DQS8 DM8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 S0 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 ZQ DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 ZQ DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 ZQ DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 ZQ DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D8 ZQ DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQS6 DQS6 DM6 DQS7 DQS7 DM7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 ZQ DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 ZQ DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 ZQ DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 ZQ VDDSPD VDD/VDDQ VREFDQ VREFCA VSS SPD D0-D8 D0-D8 D0-D8 D0-D8 BA0-BA2 A0-A14 RAS CAS WE ODT0 CKE0 CK0 CK0 RESET BA0-BA2: SDRAM D0-D8 A0-A14: SDRAM D0-D8 RAS: SDRAM D0-D8 CAS: SDRAM D0-D8 WE: SDRAM D0-D8 ODT: SDRAM D0-D8 CKE: SDRAM D0-D8 CK: SDRAM D0-D8 CK: SDRAM D0-D8 RESET: SDRAM D0-D8 Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of the JEDED document. 5. For each DRAM, a unique ZQ resistor is connected to GND. The ZQ resistor is 240O±1%. 6. Refer to associated figure for SPD details. www.swissbit.com eMail: [email protected] Page 5 of 16 5 Page Data Sheet Rev.1.0 16.09.2013 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V) AC CHARACTERISTICS PARAMETER Exit reset from CKE HIGH to a valid command SYMBOL tXPR Begin power supply ramp to power supplies stable RESET# LOW to power supplies stable RESET# LOW to I/O and RTT High-Z Exit precharge power-down to any non-READ command CKE minimum high/low time tVDDPR tRPS tIOz tXP tCKE 12800 CL11 MIN MAX max 5nCK, tRFC + 10ns - - 200 0 200 - max 3nCK,6ns max 3nCK, 5ns 20 - - 10600 CL9 MIN MAX max 5nCK, tRFC + 10ns - - 200 Unit tCK ms - 200 ms - max 3nCK,6ns max 3nCK, 5.625ns 20 - - ns tCK tCK Temperature Sensor with Serial Presence-Detect EEPROM SCL EVENT R1 0Ω WP/ EVENT SA0 SA1 SA2 SA0 SA1 SDA JEDEC JC-42.4 compliant Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: [email protected] Page 11 of 16 11 Page

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