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PDF LTC3330 Data sheet ( Hoja de datos )
| Número de pieza | LTC3330 | |
| Descripción | Energy Harvesting DC/DC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC3330 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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FEATURES
LTC3330
Nanopower Buck-Boost
DC/DC with Energy Harvesting
Battery Life Extender
DESCRIPTION
n Dual Input, Single Output DC/DCs with Input
Prioritizer
Energy Harvesting Input: 3.0V to 19V Buck DC/DC
Primary Cell Input: 1.8V to 5.5V Buck-Boost DC/DC
n Zero Battery IQ When Energy Harvesting Source is
Available
n Ultralow Quiescent Current: 750nA at No-Load
n Low Noise LDO Post Regulator
n Integrated Supercapacitor Balancer
n Up to 50mA of Output Current
n Programmable DC/DC and LDO Output Voltages,
Buck UVLO, and Buck-Boost Peak Input Current
n Integrated Low Loss Full-Wave Bridge Rectifier
n Input Protective Shunt: Up to 25mA at VIN ≥ 20V
n 5mm × 5mm QFN-32 Package
APPLICATIONS
n Energy Harvesting
n Solar Powered Systems with Primary Cell Backup
n Wireless HVAC Sensors and Security Devices
n Mobile Asset Tracking
The LTC®3330 integrates a high voltage energy harvesting
power supply plus a DC/DC converter powered by a primary
cell battery to create a single output supply for alternative
energy applications. The energy harvesting power sup-
ply, consisting of an integrated full-wave bridge rectifier
and a high voltage buck converter, harvests energy from
piezoelectric, solar, or magnetic sources. The primary cell
input powers a buck-boost converter capable of opera-
tion down to 1.8V at its input. Either DC/DC converter
can deliver energy to a single output. The buck operates
when harvested energy is available, reducing the quiescent
current draw on the battery to essentially zero, thereby
extending the life of the battery. The buck-boost powers
VOUT only when harvested energy goes away.
A low noise LDO post regulator and a supercapacitor
balancer are also integrated, accommodating a wide range
of output storage configurations. Voltage and current set-
tings for both inputs and outputs are programmable via
pin-strapped logic inputs. The LTC3330 is available in a
5mm × 5mm QFN-32 package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
+ 3V TO 19V
SOLAR
PANEL
–
22µF
25V
4.7µF, 6.3V
AC1
VIN
1µF
6.3V
CAP
VIN2
AC2
SW
LTC3330
SWA
SWB
VOUT
LDO_IN
+ PRIMARY
CELL
1.8V TO 5.5V
4.7µF
6.3V
3
3
3
4
BAT
OUT[2:0]
LDO[2:0]
IPK[2:0]
UV[3:0]
SCAP
BAL
EH_ON
PGVOUT
PGLDO
LDO_EN
LDO_OUT
GND VIN3
22µH
22µH
PIEZO
MIDE
V25W
10mF
2.7V
10mF
2.7V
OPTIONAL
1.8V TO 5V
50mA
47µF
6.3V
1.2V TO 3.3V
50mA
1µF 22µF
6.3V 6.3V
OUTPUT VOLTAGE
50mV/DIV
AC-COUPLED
Extended Battery Life with
Energy Harvesting
EH_ON
2V/DIV
0V
IBAT
100mA/DIV
0A
BAT = 3.6V
VOUT = 1.8V
ILOAD = 50mA
ACTIVE ENERGY
HARVESTER
REDUCES BATTERY
CURRENT TO ZERO
200µs/DIV
3330 TA01b
3330 TA01a
For more information www.linear.com/LTC3330
3330fa
1
1 page  
LTC3330
E LECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature
otherwise specified.
range,
otherwise
specifications
are
at
TA
=
25°C
(Note
2).
VIN
=
5V,
BAT
=
3.6V,
SCAP
=
OV,
LDO_IN
=
0V
unless
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
RN_BB
Buck-Boost NMOS Input and Output Switch
On-Resistance
IPK2 = 1
IPK2 = 0
0.6 Ω
3.8 Ω
ILEAK(P)
ILEAK(N)
PMOS Switch Leakage
NMOS Switch Leakage
Maximum Buck Duty Cycle
Buck/Buck-Boost Regulators
Buck/Buck-Boost Regulators
Buck/Buck-Boost Regulators
–20
–20
l 100
20 nA
20 nA
%
VLDO_IN
ILDO_IN
ILDO_OUT
LDO_OUT
LDO_IN Input Range
LDO_IN Quiescent Current
LDO_OUT Leakage Current
Regulated LDO Output Voltage
l 1.8V
5.5V
LDO_IN = 5.0V, ILDO_OUT = 0mA
LDO_OUT = 3.3V, LDO[2:0] = 110
400 600
100 150
Error as a Percentage of Target, 100µA
Load
–2.0
l –3.0
2.0
3.0
V
nA
nA
%
%
LDO Line Regulation (1.8V to 5.5V)
LDO_OUT = 1.2V, 10mA Load
2 mV/V
LDO Load Regulation (10µA to 10mA)
LDO_IN = 5.0V, LDO_OUT = 3.3V
0.5 mV/mA
LDO Dropout Voltage
LDO_OUT = 3.3V, 10mA LOAD
50 mV
RP_LDO
LDO PMOS Switch On-Resistance
LDO Current Limit
LDO_IN = 3.3V, ILDO_OUT = 10mA
LDO_IN = 5.0V
5
50
Ω
mA
PGLDO Rising Threshold
As a Percentage of the 3.3V LDO_OUT
l 88
92
96
Target
%
PGLDO Falling Threshold
As a Percentage of the 3.3V LDO_OUT
l 86
90
94
Target
%
VSCAP
ISCAP
ISOURCE
ISINK
VBAL
VIH
Supercapacitor Balancer Input Range
Supercapacitor Balancer Quiescent Current
Supercapacitor Balancer Source Current
Supercapacitor Balancer Sink Current
Supercapacitor Balance Point
Digital Input High Voltage
SCAP = 5.0V
SCAP = 5.0V, BAL = 2.4V
SCAP = 5.0V, BAL = 2.6V
Percentage of SCAP Voltage
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
l 2.5
5.5
150 225
10
10
l 49 50 51
l 1.2
V
nA
mA
mA
%
V
VIL Digital Input Low Voltage
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
l
0.4 V
IIH Digital Input High Current
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
0 10
nA
IIL Digital Input Low Current
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
0 10
nA
VOH PGVOUT, PGLDO Output High Voltage
EH_ON Output High Voltage
BAT = 5V, 1µA Out of Pin
VIN = 6V, 1µA Out of Pin
VOL PGVOUT, PGLDO, EH_ON Output Low Voltage BAT = 5V, 1µA into Pin
l 4.0
l 3.8
l
V
V
0.4 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3330E is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3330E is guaranteed to meet specifications from 0°C to
85°C. The LTC3330I is guaranteed over the –40°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 3: TJ is calculated from the ambient TA and power dissipation PD
according to the following formula: TJ = TA + (PD • θJA).
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The PGVOUT Rising threshold is equal to the sleep threshold. See
VOUT specification.
For more information www.linear.com/LTC3330
3330fa
5
5 Page 
LTC3330
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
ILDO_IN vs LDO_IN
900
800 125°C
700
600 85°C
500
400 25°C
300
200 –40°C
100
0
1.5 2.5 3.5 4.5 5.5
LDO_IN (V)
3330 G46
LDO_OUT vs Temperature,
LDO_OUT = 3.3V
3.36
LDO_IN = 3.6V, 100µA LOAD
3.34
3.32
3.30
3.28
3.26
3.24
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
3330 G49
LDO Load Regulation, 1.2V
1.224
1.218
1.212
1.206
LDO_IN = 5V
1.200
1.194
1.188
LDO_IN = 1.8V
1.182
1.176
1µ
10µ 100µ 1m
ILOAD (A)
10m 100m
3330 G47
LDO Load Regulation, 3.3V
3.36
3.34
3.32 LDO_IN = 5V
3.30
LDO_IN = 3.6V
3.28
3.26
3.24
1µ
10µ 100µ 1m
ILOAD (A)
10m 100m
3330 G50
LDO Line Regulation, 1.2V
1.224
1.218
1.212
1.206
1.200
1.194
LOAD = 100µA
LOAD = 10mA
1.188
1.182
1.176
1.8 2.2 2.6
3 3.4 3.8 4.2 4.6 5
LDO_IN (V)
3330 G48
LDO Line Regulation, 3.3V
3.36
3.34
3.32
LOAD = 100µA
3.30
LOAD = 10mA
3.28
3.26
3.24
3.4 3.6 3.8
4 4.2 4.4 4.6 4.8 5
LDO_IN (V)
3330 G51
LDO Start-Up
LDO_OUT
VOLTAGE
1V/DIV
0V
LDO_EN
VOLTAGE
5V/DIV
0V
2ms/DIV
LDO_IN = 5V, LDO[2:0] = 110
CLDO_OUT = 22µF
3330 G52
LDO Load Step
LDO_OUT
VOLTAGE
AC-COUPLED
20mV/DIV
LOAD
CURRENT
50mA/DIV
0mA
2ms/DIV
LDO_IN = 5V, LDO_OUT = 3.3V
CLDO_OUT = 33µF
LOAD STEP BETWEEN 1mA AND 50mA
3330 G53
For more information www.linear.com/LTC3330
3330fa
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3330.PDF ] | |
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