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PDF SGP100 Data sheet ( Hoja de datos )
| Número de pieza | SGP100 | |
| Descripción | Primary-side-control PWM Controller | |
| Fabricantes | System General | |
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Primary-side-control PWM Controller SGP
Product Specification
100
FEATURES
Constant-voltage (CV) and constant-current (CC)
control without secondary-feedback circuitry
Green-mode function: PWM frequency linearly
decreasing
Fixed PWM frequency at 42kHz with frequency
hopping to solve EMI problems
Low start-up current: 10μA (typical)
Low operating current: 6.5mA (typical)
Peak-current-mode control in CV mode
Cycle-by-cycle current limiting
VDD over-voltage protection with latch (OVP)
VDD under-voltage lockout (UVLO)
Gate output maximum voltage clamped at 18V
Fixed over-temperature protection with latch
APPLICATIONS
Battery chargers for cellular phones, cordless phones,
PDA, digital cameras, and power tools
Replacement for linear transformer and RCC SMPS
applications. The result is a low-cost, smaller and lighter
charger than a conventional design or a linear transformer.
To minimize t he s tandby po wer co nsumption, t he
proprietary g reen-mode funct ion pr ovides o ff-time
modulation t o linea rly d ecrease P WM f requency under
light-load conditions. Th is green-mode fun ction all ows
the power s upply to meet p ower conservation
requirements. The s tart-up curr ent i s onl y 10µA, which
allows large start-up resistance for further power saving.
A charger ca n be implemented w ith few ex ternal
components a nd mi nimal c ost. A t ypical output C V/CC
characteristic envelope is shown in Figure 1.
Vo(V)
+/- 10%
DESCRIPTION
This highl y int egrated PWM c ontroller p rovides s everal
features to enhance t he per formance of low-power
flyback converters. Th e p atented topology o f SGP100
enables si mplified circ uit design f or battery charger
+/- 10%
Io(mA)
Figure 1. Typical Output V-I Characteristic
TYPICAL APPLICATION
© System General Corp.
Version 1.1.1 (IAO33.0042.B1)
-1-
www.sg.com.tw • www.fairchildsemi.com
September 26, 2007
http://www.Datasheet4U.com
1 page  
Primary-side-control PWM Controller SGP
Voltage-Sense Section
Symbol P arameter
TRATIO
Proportion of TON and TDIS for Brownout
Protection*
ITC-25
CV Temperature Compensation Current
* Guaranteed by design.
Test Condition
TON /TDIS
Product Specification
100
Min.
9
Typ.
1.5
10
Max. Unit
11 µA
Current-Sense Section
Symbol P arameter
ZCS Filter Resistance
TPD Propagation Delay to GATE Output
TLEB Leading-Edge Blanking Time
TMIN-N
Minimum On-time at No Load
VSLOPE Slope
Compensation*
DSAW
Duty Cycle of SAW Limiter*
VTH-VA
Valley Threshold Voltage for Current Limit
VTH-FT
Flat threshold Voltage for Current Limit
* Guaranteed by design.
Test Condition
TMIN-N-TPD 825
Min.
Typ.
Max.
Unit
2 kΩ
150 200 ns
1025
1225
ns
1075
1200
1350
ns
0.37 0.40 0.43 V
35 40 45 %
VTH-FT - 0.4 VTH-FT - 0.25 VTH-FT - 0.1 V
1.2 1.3 1.5 V
VTH −FT
40%
VTH −VA
DCYMAX
Saw Limiter
Voltage Error Amplifier Section
Symbol P arameter
VVR Reference Voltage
VN Green-Mode Starting Voltage
VG G
SG
IV-SINK
reen-Mode Ending Voltage
Green-Mode Frequency Decreasing Rate
Output Sink Current
IV-SOURCE O
VV-HIGH
utput Source Current
Output High Voltage
Test Condition
FS=FOSC-2KHz
FS=1KHz
SG=(FOSC-3KHz)/(VN-VG)
VVS=3V, VCOMV=2.5V 85
VVS=2V, VCOMV=2.5V
VVS=2.3V 4.
Min.
2.475 2.
1.55 1.
25
85
5
Typ.
500 2.
70 1.
0.55
35
100
100
Max.
525
85
0.90
45
115
115
Unit
V
V
V
Hz/mV
µA
µA
V
Current Error Amplifier Section
Symbol Par ameter
VIR
II-SINK Out
II-SOURCE Out
VI-HIGH
Reference Voltage
put Sink Current
put Source Current
Output High Voltage
Test Condition
VCS=3V, VCOMI=2.5V
VCS=0.5V, VCOMI=2.5V
VCS=0.5V 4.
Min.
2.475 2.
40 60
40
5
Typ.
500 2.
60
Max.
525
80 µA
80
Unit
V
µA
V
© System General Corp.
Version 1.1.1 (IAO33.0042.B1)
- 5 - www.sg.com.tw • www.fairchildsemi.com
September 26, 2007
5 Page 
Primary-side-control PWM Controller SGP
Product Specification
100
Temperature Compensation
The SGP100 has buil t-in temperat ure compensation
circuitry to provide constant reliable voltage regulation at
differing a mbient te mperatures. This internal p ositive
temperature coefficient (PT C) c ompensation current i s
used to compensate f or the temp erature due to the
forward-voltage drop of t he diod e output. Th e i nternal
PTC current passes through the external resistor (R1). The
value of R1 determines t he t emperature compensation
amount. T he suggested value f or R 1 is 1 0~20KΩ with a
+/-1% tolerance value.
Temperature
Compensation
PTC
Vs
SGP100
R1
10k~20k 1±%
Auxiliary
Winding
+
VR1
−
Figure 4. Temperature Compensation
VDD Over-Voltage Protection
VDD o ver-voltage pr otection prevents damage d ue to
over-voltage c onditions. When t he voltage V DD exce eds
28V due to abnormal conditions, PWM output is latched
off. Over-voltage conditions ar e usually cau sed b y open
feedback loops.
Over-Temperature Protection (OTP)
The SGP100 has a built-in temperature sensing circuit to
shut down the PWM output then enters latch mode once
the junction temperature exceeds 150°C. When the PWM
output shuts down, the VDD voltage gradually drops to the
UVLO voltage. T he PWM co ntroller does n ot r elease
latch mode until the AC is unplugged.
Gate Output
The SGP100 BiCMOS ou tput st age i s a fast to tem pole
gate driver. Cross conduction is avoided to minimize heat
dissipation, in crease e fficiency, a nd enhance reliability.
The output driver i s clamped b y an i nternal 18V Zener
diode to protect p ower MOSFET trans istors from
undesired over-voltage gate signals.
Leading-Edge Blanking
Each time the p ower MOSFET is switched on, a t urn-on
spike occurs at the s ense r esistor. To a void premature
termination of the switching pulse, a 150ns leading-edge
blanking time is bui lt in. Convention al RC filtering c an
therefore be om itted. During t his bl anking pe riod, the
current-limit comparator is disabled and cannot switch off
the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16V/6.75V. D uring start-up, the hold-u p capacitor must
be charged to 16V through the start-up resistor, so that the
SGP100 is en abled. T he hold-up ca pacitor con tinues t o
supply V DD until p ower c an be delivered fr om the
auxiliary winding of the main transformer. VDD must not
drop be low 6 .75V d uring t his start-up process. Th is
UVLO hysteresis window ensures that hold-up capacitor
is adequate to supply VDD during start-up.
Built-in Slope Compensation
The s ensed vo ltage across the cu rrent-sense res istor i s
used for current mode control and pulse-by-pulse current
limiting. B uilt-in slop e c ompensation i mproves sta bility
and prevent sub-harmonic oscillations due to peak-current
mode control. The SGP100 has a s ynchronized,
positively-sloped ramp built-in at each switching cycle.
Noise Immunity
Noise fr om t he cu rrent sense o r the c ontrol signal c an
cause s ignificant pulse wi dth j itter. W hile s lope
compensation h elps all eviate th ese pr oblems, further
precautions should s till be taken. G ood p lacement a nd
layout practices should be followed. Avoiding long PCB
traces and c omponent lea ds, locating compen sation a nd
filter c omponents near th e S GP100, and inc reasing t he
power MOS gate resistance improves performance.
© System General Corp.
Version 1.1.1 (IAO33.0042.B1)
- 11 -
www.sg.com.tw • www.fairchildsemi.com
September 26, 2007
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SGP100.PDF ] | |
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