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Número de pieza | TC94A48FG | |
Descripción | Single-chip Audio Digital Signal Processor | |
Fabricantes | Toshiba Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de TC94A48FG (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC94A48FG
TC94A48FG
Single-chip Audio Digital Signal Processor
The TC94A48FG i s a si ngle-chip au dio Di gital Si gnal
Processor, incorporating two cha nnels A D co nverter and
six channels DA converter.
It ca n re alize m any a pplications, including s ound fi eld
control, s uch as ha ll s imulation, di gital filters, such a s
equalizers, surround sound, base boost and more.
Features
• Incorporates a 1-bit Σ-∆ AD converter (2 channels).
P-LQFP64-1010-0.50E
THD+N: -78 dB (typ.), S/N ratio: 92 dB (typ.)
• Incorporates a multi-bit Σ-∆ DA converter (6 channels).
Weight: 0.4 g (typ.)
THD+N: -88 dB (typ.), S/N ratio: 98 dB (typ.)
• Digital input/output ports
Four input ports (8 channels)
Four output ports (8 channels)
• The DSP block specifications are as follows:
Data bus
: 24 bits
M ultiplier/adder
: 24 bits × 24 bits + 51 bits → 51 bits
Accumulator
: 51 bits (sign extension: 4 bits)
Program ROM
: 3072 words × 16 bits
Program RAM
: 1024 words × 16 bits
XRAM
: 4096 words × 24 bits
YRAM
: 1024 words × 24 bits
CROM
: 1024 words × 24 bits
• The microcontroller interface can be selected between serial mode and I2C bus mode.
• Operating supply voltage: 3.3 V (some pins accept 5 V)
• CMOS silicon structure supports high speed.
• The package is a 64-pin LQFP (0.5-mm pitch) package.
1 2005-09-28
http://www.Datasheet4U.com
1 page TC94A48FG
Description of Operation
1. T iming System
The TC94A48FG uses pulses from the XI-XO pins as the reference clock. The system is divided into blocks
that use the reference clock directly or by dividing its frequency and blocks that operate on a clock the PLL
generates based on the crystal resonation clock. The analog and microcontroller interface blocks operate on
the crystal resonation clock while the DSP block operates on the PLL-generated clock.
Crystal
Input=
256fs
PLL
Divider
Dividing
Clock for DSP
PLL-generated
Clock for Analog Block (256fs)
Clock for Analog Block (256fs or 512fs)
Timing output to pins
(LRCKO,BCKO,MCKO)
Crystal precision
Figure 1 Timing System
The system can divide the clock from the crystal and provide three types of clock from output pins.
Xi
Xo
fxi = 11.2896MHz
(44.1kHz×256)
MCKO Clock LRCKO, BCKO Clock
fs256
×1/2 ~ ×1/512
fs128~fs0.5
×1/M
REFCK
VARCK
Phase
Comp.
VCO
×1/N
PLL
×1/J
Figure 2 Block diagram of clock generator circuit
ADC, DAC
MAF, ΣΔ
Audio I/F
MCU I/F
DSP
5 2005-09-28
5 Page TC94A48FG
1.5.2 Audio Serial Data Output Format
The valid part of data is the same as that for the input format. The TC94A48FG supports MSB-first
output only. In slave mode, it supports all setting formats for the number of bit clock slots. In master
mode, it does not support 24 slots.
M =MSB L =LSB
MO
DE
Number Data Word
of Length
SLOT (bits)
Format
0
16
1
16
I2S
=fixed to “0” (data sent from DSP is ignored)
Timing Chart
ML
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Remarks
Initial
value
ML
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2
3 16
4 24
I2S
M
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
M
15
M
15
L
L
0
L
0
Unavailable
in master
mode(Note)
5
24
M
23
6 I2S
M
23
L
0
L
0
7
ML
15 0
8 16
ML
15 0
9
32
10
I2S
M
15
M
23
L
0
L
0
11 24
M
23
L
0
12 I2S
M
23
L
0
Note 5: These formats cannot be used in master mode (when LRCK and BCK are supplied to external devices).
11 2005-09-28
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet TC94A48FG.PDF ] |
Número de pieza | Descripción | Fabricantes |
TC94A48FG | Single-chip Audio Digital Signal Processor | Toshiba Semiconductor |
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