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PDF MP4651 Data sheet ( Hoja de datos )
| Número de pieza | MP4651 | |
| Descripción | Off Line LED Driver | |
| Fabricantes | MPS | |
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MP4651
The Future of Analog IC Technology
DESCRIPTION
The MP4651 is a high performance off-line LED
driver designed for powering the LEDs especially
for high power isolated application.
The MP465 1 u tilizes f ixed operating f requency
PWM control. It outputs two 180 degree phase
shifted driving signals for vario us external
power stag es. Its enh anced 9V gate driver
provides adequate driving capability for the
external MOSFETs a nd directly drives th e
external gate driving transformer.
The MP4651 implements fast and high contrast
ratio PWM dimming to the
LEDs. PW M
dimming is controlled with either an external DC
voltage or PWM signa l. The burst dimming
frequency can be synchronized to an externa l
synchronizing signal.
The Bu ilt-in fau lt man agement fe atures inclu de
open LED p rotection, short LED protection, over
voltage pr otection, a nd over temperature
protection. T he protection in terface is flexible for
various setups an d is ea sy to use. MP465 1
integrates a delay timer to recover the system.
The MP465 1 is available in a 16-pin SOIC
package.
Off Line LED Driver
FEATURES
• 9V Enhanced Gate Driver
• Programmable Fixed Operating Frequency
• Input Voltage Range from 9V to 30V
• DC or PWM Input Dimming Control
• Burst Dimming Frequency Synchronization
• Smart Fault Protection Interface
• Built-in Fault Management
• Built-in Delay Timer for System Recovery
• Available in a SOIC16 Package
APPLICATIONS
• LCD TV and LCD Monitor
• Flat Panel Video Displays
• LED Lighting Applications
For MPS green status, please vis it MP S we bsite un der Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The M P4651 i s covered b y U S Patents 6,683,422, 6,316,881, and
6,114,814. Other Patents Pending.
MP4651 Rev.1.0
1/13/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
1
http://www.Datasheet4U.com
1 page  
MP4651—OFF LINE LED DRIVER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameter
Symbol Conditio n
Fault Timer (FT)
Threshold
Source Current
Comp
Clamp Voltage
Reference Current
Pull Down Current at Fault
Condition
Vth(FT)
ISOURCE(FT)
VCOMP
ICOMP+
ICOMP-FAULT
Fault Mode is triggered
Burst Frequency Synchronization (SYNC)
High logic level
VSYNC-H
Low logic level
VSYNC-L
Pulse width
tsync
Synchronizing Frequency
fSYNC
DC input burst dimming,
Compared to the
frequency fBFS set by
BFS pin R and C
Fault Detection Threshold (SSD, FB)
SSD Threshold
SSD Detection Delay Time
FB threshold
FB Detection Delay Time
VSSD
TD SSD
VFB th
TD FB
Output Gate Driver (VCC)
Voltage V
Current I
VCC No
VCC
load
Min Typ
2.2 2.4
8
0.60
20
30
1.4
6 10
110% 120%
2.22 2.36
7
1.1 1.2
7
8.7 9.7
20
Max Units
2.6 V
µA
V
µA
µA
V
0.7 V
20 µs
2.55 V
µs
1.3 V
µs
10.5
V
mA
MP4651 Rev.1.0
1/13/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
5
5 Page 
MP4651—OFF LINE LED DRIVER
CBFS
=
fBurst
1− Drise
××RBFS 0.405
For Drise= 0.1, fBurst= 200Hz, then RBFS = 212k, CBFS=
52nF
For direct PWM burst dimming, pull BFS high to
VCC through a 20kΩ resistor and apply the PWM
signal to PWMIN pin.
Pin 2 (SYNC):
Burst frequency synchronization. This pin is use d
to synchronize the b urst dimming frequency.
Applying a synchronizing frequency signal with
small pulse will synchronize the burst frequency.
SYNC
Signal
A
MP4651
1 OVP
2 SYNC
3 SSD
16
GR
15
GND
GL 14
4 FB
VCC 13
5
COMP
12
VIN
6 FT
11
EN
7 PWMOUT PWMIN
8 FSET
BFS
10
9
REF
SYNC
Signal
1.2V
A
BFS
3.55V
2.4V
Burst dimming
signal
I LED
Figure 4—Synchronized DC Input Burst
Dimming
Figure 4 sh ows the synchronized D C input burst
dimming. The synchron izing signal is filtered by
a high pa ss filter. Its r ising edge is caught an d
used for synchronizing the triangle waveform on
BFS pin. The synchronizing frequen cy should be
higher than that set by BFS pin and the
amplitude of the synchronizing sign al should b e
higher than 1.4V.
Table 1—Function Mode
Function
Pin Connection
PWM BFS
SYNC
Burst Mode with DC
Input Voltage
0V to
1.2V
CBFS, RBFS
GND
Burst Mode with DC
Input Voltage and
Synchronizing
frequency
0V to
1.2V
CBFS, RBFS
R,C,D
network
Burst Mode with
External PWM Source
PWM
To VCC
through
20kΩ
resistor
GND
Burst Brightness Polarit y: 100% d uty cycle a t
PWM voltage 1.2V.
Pin 11 (EN):
Pull this pin high to enable the chip, and pull it
low to disable the chip.
Pin 12 (VIN):
Supply volta ge input. Bypass the su pply voltage
with a 0.1uF or greater ceramic cap. This ca p
should be placed close to the IC.
Pin 13 (VCC):
This pin pro vides the gate driver supply voltage,
its typical value is 9.7V. Connect a 1uF or greater
ceramic ca pacitor on this pin to bypass th e
supply voltage. This voltage is also used to
supply the external control circuit.
Pin 14(GL), Pin 16 (GR):
Gate driving signals out put. GL and GR are 180
degree pha se shifte d driving sign als. With it s
enhanced driving capability, GL and GR are able
to directly drive the externally MOSFET in the off-
line system through a gate driving transformer.
Connect two 5 Ω resist ors in ser ies with GL and
GR to reduce the EMI noise.
A 2.2nF Y capacitor is recommended to be
placed bet ween the primary ref erence gro und
and secondary reference ground.
MP4651 Rev.1.0
1/13/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MP4651.PDF ] | |
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