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PDF MP1482 Data sheet ( Hoja de datos )

Número de pieza MP1482
Descripción 2A 18V Synchronous Rectified Step-Down Converter
Fabricantes MPS 
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MP1482
The Future of Analog IC Technology
DESCRIPTION
The MP148 2 is a monolithic synchr onous buck
regulator. T he device integrates t wo 130m
MOSFETs, and provides 2A of cont inuous load
current over a wide input voltage of 4.75V to
18V. Current mode control pro
vides fast
transient re sponse and cycle-by-cycle current
limit.
An adjustab le soft-start prevents inrush current
at turn-on, and in shut down mode the supply
current drops to 1µA.
This device, available in an
8-pin SOI C
package, provides a very compact solution with
minimal external components.
2A, 18V Synchronous Rectified
Step-Down Converter
FEATURES
2A Output Current
Wide 4.75V to 18V Operating Input Range
Int egrated 130mPower MOSFET Switches
Output Adjustable from 0.923V to 15V
Up to 93% Efficiency
Programma ble Soft-Start
Stable withLow ESR Ceramic Output Capacitors
Fixed 340kHz Frequency
Cycle-by-Cycle Over Current Protection
Input Under Voltage Lockout
8–Pin SOIC
APPLICATIONS
Distributed Power Systems
Networking Systems
FPGA, DSP, ASIC Power Supplies
Green Electronics/ Appliances
Notebook Computers
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
INPUT
21
7 IN
EN
BS 3
SW
8
SS
MP1482
5
FB
GND
COMP
46
Efficiency vs
Load Current
100
95 VOUT = 3.3V
90
85 VOUT = 2.5V
80
75
70
65
60
55
50
0 0.5 1.0 1.5 2.0
LOAD CURRENT (A)
2.5
MP1482 Rev. 1.31
www.MonolithicPower.com
7/9/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
1
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MP1482 pdf
MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VO = 3.3V, L = 10µH, C1 = 10µF, C2 = 22µF, TA = +25°C, unless otherwise noted.
Steady State Test
VIN = 12V, VOUT = 3.3V
IOUT = 0A, IIN= 8.2mA
Startup through Enable
VIN = 12V, VOUT = 3.3V
IOUT = 1A (Resistance Load)
Shutdown through Enable
VIN = 12V, VOUT = 3.3V
IOUT = 1A (Resistance Load)
VIN
20mV/div.
VOUT
20mV/div.
IL
1A/div.
VSW
10V/div.
VEN
5V/div.
VOUT
1V/div.
IL
1A/div.
VSW
10V/div.
VEN
5V/div.
VOUT
2V/div.
IL
1A/div.
VSW
10V/div.
Heavy Load Operation
2A Load
VIN, AC
200mV/div.
VO, AC
20mV/div.
IL
1A/div.
VSW
10V/div.
Medium Load Operation
1A Load
Light Load Operation
No Load
VIN, AC
200mV/div.
VIN, AC
20mV/div.
VO, AC
20mV/div.
IL
1A/div.
VO, AC
20mV/div.
IL
1A/div.
VSW
10V/div.
VSW
10V/div.
Short Circuit
Protection
VOUT
2V/div.
IL
2A/div.
Short Circuit
Recovery
VOUT
2V/div.
IL
2A/div.
Load Transient
VOUT
200mV/div.
IL
1A/div.
ILOAD
1A/div.
MP1482 Rev. 1.31
www.MonolithicPower.com
7/9/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
5

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MP1482 arduino
MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER
PCB LAYOUT GUIDE
PCB layout is very imp ortant to achieve stable
operation. It is highly recommended to duplicate
EVB layout for optimum performance.
If change is necessar y, please follow these
guidelines and take Figure 4 for reference.
1) Keep the path of switching curren t short and
minimize the loop area formed by input cap,
high-side MOSFET and low-side MOSFET.
INPUT
4.75V to 18V
2) Bypass ceramic capacitors are su ggested
to be put close to the Vin Pin.
3) Ensure all f eedback co nnections a re short
and direct. Place the feedback resistors
and compensation com ponents as close to
the chip as possible.
4) Route SW away fro m sensitive analog
areas such as FB.
5) Connect IN, SW, and especia lly GND
respectively to a large copper area to cool
the chip to improve thermal performance
and long-term reliability.
C5
R4
2
7 IN
EN
1
BS 3
SW
L1
OUTPUT
MP1482
85
C1
SS
GND
FB
COMP
R1
4
C4
6
C3
R3
D1
(optional)
R2
C2
MP1482 Typical Application Circuit
R4 C3 R3
C4 R21
R1
PGND
PGND
D1
C2
C5 C1
L1
SGND
Top Layer
Bottom Layer
Figure 4—MP1482 Typical Application Circuit and PCB Layout Guide
MP1482 Rev. 1.31
www.MonolithicPower.com
7/9/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
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