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PDF MT29F32G08CBACA Data sheet ( Hoja de datos )
| Número de pieza | MT29F32G08CBACA | |
| Descripción | NAND Flash Memory | |
| Fabricantes | Micron | |
| Logotipo |  |
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Micron Confidential and Proprietary
Advance‡
32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F32G08CBACA, MT29F64G08CEACA, MT29F64G08CFACA,
MT29F128G08CXACA, MT29F64G08CECCB
Features
• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Multiple-level cell (MLC) technology
• Organization
– Page size x8: 4320 bytes (4096 + 224 bytes)
– Block size: 256 pages (1024K + 56K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 32Gb: 4096 blocks;
64Gb: 8192 blocks;
128Gb: 16,384 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 5
– Clock rate: 10ns (DDR)
– Read/write throughput per pin: 200 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
– tRC/tWC: 20ns (MIN)
• Array performance
– Read page: 50µs (MAX)
– Program page: 1300µs (TYP)
– Erase block: 3ms (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 1.7–1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 101).
• RESET (FFh) required as first command after power-
on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
– Data retention: 10 years
– Endurance: 3000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 52-pad LGA
– 48-pin TSOP
– 100-ball BGA
Note: 1. The ONFI 2.2 specification is available at
www.onfi.org.
PDF: 09005aef83f64350
l73a_32g_64g_128g_asyncsync_nand.pdf – Rev. A 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.
Free Datasheet http://www.Datasheet4U.com
1 page  
Micron Confidential and Proprietary
Advance
32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 22
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 23
Table 4: Synchronous Interface Mode Selection ............................................................................................. 33
Table 5: Command Set .................................................................................................................................. 44
Table 6: Read ID Parameters for Address 00h ................................................................................................. 50
Table 7: Read ID Parameters for Address 20h .................................................................................................. 50
Table 8: Feature Address Definitions .............................................................................................................. 51
Table 9: Feature Address 01h: Timing Mode ................................................................................................... 53
Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 53
Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 54
Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 54
Table 13: Parameter Page Data Structure ....................................................................................................... 57
Table 14: Status Register Definition ............................................................................................................... 65
Table 15: OTP Area Details ............................................................................................................................ 96
Table 16: Error Management Details ............................................................................................................. 101
Table 17: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V) .............................................................. 102
Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) .......................................................... 102
Table 19: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 103
Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 103
Table 21: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 104
Table 22: Overshoot/Undershoot Parameters ................................................................................................ 105
Table 23: Test Conditions for Input Slew Rate ................................................................................................ 106
Table 24: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 106
Table 25: Test Conditions for Output Slew Rate ............................................................................................. 107
Table 26: Output Slew Rate (VCCQ = 1.7–1.95V) .............................................................................................. 107
Table 27: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 107
Table 28: Absolute Maximum Ratings by Device ............................................................................................ 108
Table 29: Recommended Operating Conditions ............................................................................................ 108
Table 30: Valid Blocks per LUN ..................................................................................................................... 108
Table 31: Capacitance: 100-Ball BGA Package ................................................................................................ 109
Table 32: Capacitance: 48-Pin TSOP Package ................................................................................................ 109
Table 33: Capacitance: 52-Pad LGA Package .................................................................................................. 109
Table 34: Test Conditions ............................................................................................................................. 109
Table 35: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 110
Table 36: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 110
Table 37: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 111
Table 38: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 112
Table 39: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 112
Table 40: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 114
Table 41: Array Characteristics ..................................................................................................................... 117
PDF: 09005aef83f64350
l73a_32g_64g_128g_asyncsync_nand.pdf – Rev. A 3/10 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com
5 Page 
Micron Confidential and Proprietary
Advance
32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Sync Async
x8 x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
W/R#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
CLK
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Async
x8
Sync
x8
48
47
DNU/VSSQ2 DNU/VSSQ2
NC NC
46 NC
NC
45 NC
NC
44 DQ7 DQ7
43 DQ6 DQ6
42 DQ5 DQ5
41 DQ4 DQ4
40 NC
NC
39 DNU/VCCQ2 DNU/VCCQ2
38 DNU DNU
37 VCC
VCC
36 VSS
VSS
35 DNU DQS
34
33
DNU/VCCQ2 DNU/VCCQ2
NC NC
32 DQ3 DQ3
31 DQ2 DQ2
30 DQ1 DQ1
29 DQ0 DQ0
28 NC
NC
27 NC
NC
26 DNU DNU
25 DNU/VSSQ2 DNU/VSSQ2
Notes:
1. CE2# and R/B2# are available on dual die packages. They are NC for other configurations.
2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.2. If not supplying VCCQ or
VSSQ to these pins, do not use them.
PDF: 09005aef83f64350
l73a_32g_64g_128g_asyncsync_nand.pdf – Rev. A 3/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
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